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Signal Descriptions
Table 5-1.
Signal Definitions (Sheet 3 of 4)
Name
THERMTRIP#
TMS
TRST#
VCC
VCC_SENSE
VSS_SENSE
VCCPLL
VCCPWRGOOD
VDDPWRGOOD
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
VTTA
VTTD
Datasheet
Type
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its
internal clocks (thus halting program execution) in an attempt to reduce the
O
processor junction temperature. To further protect the processor, its core
voltage (V
), V
V
CC
TTA
THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is
asserted. While the assertion of the RESET# signal may de-assert
THERMTRIP#, if the processor junction temperature remains at or above the
trip level, THERMTRIP# will again be asserted after RESET# is de-asserted.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
I
tools.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
I
driven low during power on Reset.
I
Power for processor core.
VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to
O
the processor core power and ground. They can be used to sense or measure
O
voltage near the silicon.
I
Power for on-die PLL filter.
VCCPWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that BCLK, V
are stable and within their specifications. 'Clean' implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time
that the power supplies are turned on until they come within specification. The
I
signal must then transition monotonically to a high state. VCCPWRGOOD can be
driven inactive at any time, but BCLK and power must again be stable before a
subsequent rising edge of VCCPWRGOOD. In addition at the time
VCCPWRGOOD is asserted RESET# must be active. The PWRGOOD signal must
be supplied to the processor. It should be driven high throughout boundary scan
operation.
VDDPWRGOOD is an input that indicates the V
processor requires this signal to be a clean indication that the V
supply is stable and within specifications. "Clean" implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time
I
that the Vddq supply is turned on until it comes within specification. The signals
must then transition monotonically to a high state.
The PwrGood signal must be supplied to the processor.
VID[7:0] (Voltage ID) are used to support automatic selection of power supply
voltages (V
). The voltage supply for these signals must be valid before the VR
CC
can supply V
to the processor. Conversely, the VR output must be disabled
CC
until the voltage supply for the VID signals become valid. The VR must supply
the voltage that is requested by the signals, or disable itself.
VID7 and VID6 should be tied separately to V
reset (This value is latched on the rising edge of VTTPWRGOOD)
I/O
MSID[2:0] — MSID[2:0] is used to indicate to the processor whether the
platform supports a particular TDP. A processor will only boot if the MSID[2:0]
pins are strapped to the appropriate setting on the platform (see
MSID encodings). In addition, MSID protects the platform by preventing a
higher power processor from booting in a platform designed for lower power
processors.
CSC[2:0] — Current Sense Configuration bits, for ISENSE gain setting. This
value is latched on the rising edge of VTTPWRGOOD.
Power for the analog portion of the integrated memory controller, QPI and
I
Shared Cache.
Power for the digital portion of the integrated memory controller, QPI and
I
Shared Cache.
Description
, and V
must be removed following the assertion of
TTD
DDQ
, V
CC
CCPLL
DDQ
using a 1 kresistor during
SS
, V
and V
supplies
TTA
TTD
power supply is good. The
power
DDQ
Table 2-2
for
Notes
69
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