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ADLINK Technology COM-HPC-cRLS User Manual

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COM-HPC-cRLS User's Guide
COM-HPC-cRLS
Page 1
User's Guide
Revision:
Rev. 1.0
Date:
2024-12-20
Part Number:
50M-73301-1000
Copyright © 2024 ADLINK Technology, Inc.
PICMG COM-HPC R1.1

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Summary of Contents for ADLINK Technology COM-HPC-cRLS

  • Page 1 COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 COM-HPC-cRLS User’s Guide Revision: Rev. 1.0 Date: 2024-12-20 Part Number: 50M-73301-1000 Page 1 Copyright © 2024 ADLINK Technology, Inc.

  • Page 2: Revision History

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 Revision History Revision Description Date Author Initial release 2024-12-20 Page 2 Copyright © 2024 ADLINK Technology, Inc.

  • Page 3: Preface

    Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. Copyright © 2024 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. • Page 4 Copyright © 2024 ADLINK Technology, Inc.
  • Page 5 Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Page 5 Copyright © 2024 ADLINK Technology, Inc.
  • Page 6 ADLINK Technology GmbH Hans-Thoma-Strasse 8-10, D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. Page 6 Copyright © 2024 ADLINK Technology, Inc.

  • Page 7: Table Of Contents

    4.3.7 USB ....................................................................42 4.3.8 Port 80 Support on USB_PD_I2C......................................................... 45 4.3.9 SATA ....................................................................46 4.3.10 Asynchronous Serial Port ............................................................46 4.3.11 I2C ....................................................................47 4.3.12 General Purpose SPI (GP_SPI) ..........................................................47 Page 7 Copyright © 2024 ADLINK Technology, Inc.
  • Page 8 7.2.3 Board Information ..............................................................74 7.2.4 System Date and Time ............................................................75 Advanced ....................................................................75 7.3.1 CPU Configuration ..............................................................76 7.3.2 Power & Performance ............................................................. 80 7.3.3 Intel(R) Time Coordinated Computing......................................................96 Page 8 Copyright © 2024 ADLINK Technology, Inc.
  • Page 9 OEM-reserved Checkpoint Ranges ..........................................................167 9. Software Support ..........................................................168 Windows 10 IoT Enterprise 2021 LTSC 64-bit ......................................................168 Ubuntu 20.04 ..................................................................168 Yocto Project* BSP tool-based embedded Linux distribution ................................................168 10. Mechanical ............................................................... 169 Page 9 Copyright © 2024 ADLINK Technology, Inc.
  • Page 10 COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 11. Thermal ..............................................................170 11.1 Thermal Solutions ................................................................170 11.1.1 Heatspreader: HTS ..............................................................170 11.1.2 Heatsink: THS-BL ..............................................................171 11.1.3 Heatsink with Fan: THSF-BL-S ..........................................................172 Page 10 Copyright © 2024 ADLINK Technology, Inc.

  • Page 11: List Of Figures

    Figure 4 – Module feature locations (back) ..................................................57 Figure 5 – Module mechanical dimensions ..................................................169 Figure 6 – Heatspreader: HTS ......................................................... 170 Figure 7 – Heatsink: THS-BL ........................................................171 Figure 8 – Heatsink with Fan: THSF-BL-S ................................................... 172 Page 11 Copyright © 2024 ADLINK Technology, Inc.

  • Page 12: Introduction

    Introduction The COM-HPC-cRLS is a Client Type COM-HPC Size C module based on 13th Gen Intel® Core™ processors (formerly “Raptor Lake-S”). The processor offers up to 24 cores (8P-cores + 16 E-cores) at 5.2/4.2GHz boost frequency, and puts an emphasis on industrial-class reliability and longevity.

  • Page 13: Specifications

    Up to 128GB (4x 32GB) DDR5 SODIMM in 4x DIMM sockets (ECC or non-ECC) Up to 4000 MT/s in 4x sockets (2x on top, 2x at bottom), configured as: 2 DIMMs per channel 1R – 4000MT/s • 2 DIMMs per channel 2R – 3600MT/s • Page 13 Copyright © 2024 ADLINK Technology, Inc.

  • Page 14: Expansion Buses

    1x PCI Express x4 Gen4: Lanes 12-15 (configurable to 1 x4, 2 x2, 4 x1) 1x PCI Express x4 Gen4: Lanes 32-35 (configurable to 1 x4, 2 x2, 4 x1) 1x PCI Express x4 Gen4: Lanes 36-39 (configurable to 1 x4, 2 x2, 4 x1) Page 14 Copyright © 2024 ADLINK Technology, Inc.

  • Page 15: Ethernet Nbase-T

    4x USB2.0/1.1 (USB 4, 5, 6, 7) SuperSpeed, High-Speed, Full-Speed, and Low-Speed USB signaling Note: Only supports 2x USB3.x/2.0/1.1 (USB 0, 1) if chipset H610E used. USB3.2 supports up to 10Gbits if R680E/Q670E used (dependent on carrier design). Page 15 Copyright © 2024 ADLINK Technology, Inc.

  • Page 16: Trusted Platform Module (Tpm)

    Type: TPM 2.0 (SPI bus based) 2.6 SEMA Board Controller Supports Voltage/current monitoring, Power sequence debug support, Logistics and forensic information, General purpose I2C, Failsafe BIOS (dual BIOS, build, optional support), Watchdog timer, and Fan control Page 16 Copyright © 2024 ADLINK Technology, Inc.

  • Page 17: Debug

    PICMG COM-HPC Revision 1.1, Client Type, Size C 160 x 120 mm Operating Temperature Standard 0°C to 60°C (Standard Voltage Input) Storage: -20°C to 80°C Humidity 5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating) Page 17 Copyright © 2024 ADLINK Technology, Inc.
  • Page 18 Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D HALT tested Thermal Stress, Vibration Stress, Thermal Shock, and Combined Test Page 18 Copyright © 2024 ADLINK Technology, Inc.

  • Page 19: Block Diagram

    BOOT_SPI GP_SPI SMBus 1 PCIe GEN4 x4 SMBus EEPROM I2C_0 2 MIPI-CSI I2C_1 2x HSUART eSPI 1DPC Style 12xGPIO Embedded connector 2xUART Controller LM73 eSPI (board) Figure 1 – Module function diagram Page 19 Copyright © 2024 ADLINK Technology, Inc.

  • Page 20: Pinout And Signal Descriptions

    The table below is a comprehensive list of all signal pins supported on the dual 400-pin COM-HPC connectors as defined for Client Type in the PICMG COM-HPC R1.1 specification. Signals described in the specification but not supported on the COM-HPC-cRLS are marked by STRIKETHROUGH.
  • Page 21 DDI1_PAIR1+ USB23_OC# DDI1_DDC_AUX_SEL USB01_OC# DDI0_HPD DDI0_PAIR2- DDI1_PAIR2- SML1_CLK DDI1_HPD DDI0_PAIR2+ DDI1_PAIR2+ SML1_DAT eDP_HPD PMCALERT# eDP_VDD_EN DDI0_PAIR3- DDI1_PAIR3- SML0_CLK eDP_BKLT_EN DDI0_PAIR3+ DDI1_PAIR3+ SML0_DAT eDP_BKLTCTL USB_PD_ALERT# AC_PRESENT eDP_AUX- USB_PD_I2C_CLK USB1_AUX- RSVD eDP_AUX+ USB_PD_I2C_DAT USB1_AUX+ Page 21 Copyright © 2024 ADLINK Technology, Inc.
  • Page 22 PCIe08_RX- PCIe00_TX- PCIe08_TX- PCIe08_RX+ PCIe00_RX- PCIe00_TX+ PCIe08_TX+ PCIe00_RX+ PCIe09_RX- PCIe01_TX- PCIe09_TX- PCIe09_RX+ PCIe01_RX- PCIe01_TX+ PCIe09_TX+ PCIe01_RX+ PCIe10_RX- PCIe02_TX- PCIe10_TX- PCIe10_RX+ PCIe02_RX- PCIe02_TX+ PCIe10_TX+ PCIe02_RX+ PCIe11_RX- PCIe03_TX- PCIe11_TX- PCIe11_RX+ PCIe03_RX- PCIe03_TX+ PCIe11_TX+ PCIe03_RX+ Page 22 Copyright © 2024 ADLINK Technology, Inc.
  • Page 23 GPIO_06 GPSPI_MISO* I2C0_DAT NBASET0_MDI3- GPIO_07 GPSPI_CS0#* I2C0_ALERT# NBASET0_MDI3+ GPIO_08 GPSPI_CS1# I2C1_CLK GPIO_09 GPSPI_CS2# I2C1_DAT NBASET0_LINK_MAX# GPIO_10 GPSPI_CS3# NBASET0_SDP * NBASET0_LINK_MID# GPIO_11 GPSPI_CLK* NBASET0_CTREF NBASET0_LINK_ACT# A100 TYPE0 B100 GPSPI_ALERT#* C100 TYPE1 D100 TYPE2 Page 23 Copyright © 2024 ADLINK Technology, Inc.
  • Page 24 PCIe33_TX+* PCIe41_RX+ PCIe34_RX-* PCIe42_TX- PCIe34_TX-* PCIe34_RX+* PCIe42_RX- PCIe42_TX+ PCIe34_TX+* PCIe42_RX+ PCIe35_RX-* PCIe43_TX- PCIe35_TX-* PCIe35_RX+* PCIe43_RX- PCIe43_TX+ PCIe35_TX+* PCIe43_RX+ PCIe36_RX-* PCIe44_TX- PCIe36_TX-* PCIe36_RX+* PCIe44_RX- PCIe44_TX+ PCIe36_TX+* PCIe44_RX+ PCIe37_RX-* PCIe45_TX- PCIe37_TX-* PCIe37_RX+* PCIe45_RX- PCIe45_TX+ Page 24 Copyright © 2024 ADLINK Technology, Inc.
  • Page 25 PCIe29_RX+ PCIe22_RX- PCIe30_TX- PCIe22_TX- PCIe22_RX+ PCIe30_RX- PCIe30_TX+ PCIe22_TX+ PCIe30_RX+ PCIe23_RX- PCIe31_TX- PCIe23_TX- PCIe23_RX+ PCIe31_RX- PCIe31_TX+ PCIe23_TX+ PCIe31_RX+ RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD NBASET1_MDI0- CSI1_RX0- RSVD NBASET1_MDI0+ CSI0_RX0- CSI1_RX0+ Page 25 Copyright © 2024 ADLINK Technology, Inc.
  • Page 26 SNDW/I2S/DMIC is dependent on device on carrier board and by project basis. UART 0, 1_CTS#, RTS# only available if routed from PCH and by project basis. GP_SPI by project basis. 4x USB 3.2 Gen2x2 require BIOS modification and by project basis. Page 26 Copyright © 2024 ADLINK Technology, Inc.

  • Page 27: Signal Terminology Descriptions

    Pull-down strap. A Module output pin that is either tied to GND or is not connected. Used to signal Module capabilities to the Carrier Board. PU (pull-up) resistor on module PD (pull-down) resistor on module Page 27 Copyright © 2024 ADLINK Technology, Inc.

  • Page 28: Signal Descriptions On J1/J2 Connectors

    Ethernet controller is capable of. 20 mA or more current sink capability at VOL of 0.4V max. 20 mA or more current source capability at VOH of 2.4V min. Page 28 Copyright © 2024 ADLINK Technology, Inc.
  • Page 29 20 mA or more current source capability at VOH of 2.4V min. NBASET1_LINK_MID# NBASE-T Ethernet Controller MID Speed Link indicator, active low. If O 3.3VSB active, the link is established but at a speed lower than what the Page 29 Copyright © 2024 ADLINK Technology, Inc.

  • Page 30: Digital Display Interface (Ddi)

    If this input is unconnected on the Carrier, the AUX pair is used for the DP AUX+/- signals. If pulled or driven high on the Carrier, the AUX pair contains the HDMI[0:2] I2C CRTL_CLK and CTRL_DAT signals. Page 30 Copyright © 2024 ADLINK Technology, Inc.
  • Page 31 HDMI/DVI I2C data if DDI[0:2]_DDC_AUX_SEL is pulled high DDI1_SCL_AUX+ DP AUX+ function if DDI[0:2]_DDC_AUX_SEL is a no I/O PCIE AC coupled on Module for DP connect or driven to GND on the Carrier. 100K Page 31 Copyright © 2024 ADLINK Technology, Inc.
  • Page 32 AC coupled on Module for DP connect or driven to GND on the Carrier. 100K HDMI/DVI I2C clock if DDI[0:2]_DDC_AUX_SEL is pulled or driven high on the Carrier. DDI2_HPD DDI Hot-Plug Detect I 3.3V 100K Page 32 Copyright © 2024 ADLINK Technology, Inc.
  • Page 33 TMDS0_DATA2+ DDI0_PARI0- DP0_LANE0- TMDS0_DATA2- DDI0_PARI1+ DP0_LANE1+ TMDS0_DATA1+ DDI0_PARI1- DP0_LANE1- TMDS0_DATA1- DDI0_PARI2+ DP0_LANE2+ TMDS0_DATA0+ DDI0_PARI2- DP0_LANE2- TMDS0_DATA0- DDI0_PARI3+ DP0_LANE3+ TMDS0_CLK+ DDI0_PARI3- DP0_LANE3- TMDS0_CLK- DDI0_HPD DP0_HPD HDMI0_HPD DDI0_SLC_AUX+ DP0_AUX+ HDMI0_CTRCLK DDI0_SDA_AUX- DP0_AUX- HDMI0_CTRDAT DDI0_DDC_AUX_SEL Page 33 Copyright © 2024 ADLINK Technology, Inc.

  • Page 34: Embedded Display Port (Edp) / Mipi-Dsi

    DSI display (that has it’s own display controller and frame buffer) coordinating with the host display controller Note: This platform does not support MIPI-DSI interface, thus the mapping table between eDP and DSI is not mentioned here. Page 34 Copyright © 2024 ADLINK Technology, Inc.

  • Page 35: Serial Audio Interface

    Description PU / Comment SNDW_DMIC_DAT0 Bi-directional PCM audio data I/O 1.8VSB PU 10K By project basis discussion SNDW_DMIC_DAT1 SNDW_DMIC_CLK0 Clock for Soundwire transactions O 1.8VSB PU 10K By project basis discussion SNDW_DMIC_CLK1 Page 35 Copyright © 2024 ADLINK Technology, Inc.

  • Page 36: Camera Serial Interface (Csi)

    PCIe05_TX- PCIe06_TX+ PCIe lane 6-7 not supported PCIe06_TX- PCIe07_TX+ PCIe07_TX- PCIe00_RX+ PCI Express Differential Receive Pairs 0-7 I PCIe AC coupled off Module PCIe00_RX- PCIe Group 0 Low PCIe01_RX+ PCIe01_RX- PCIe02_RX+ PCIe02_RX- Page 36 Copyright © 2024 ADLINK Technology, Inc.
  • Page 37 PCIe08_RX- PCIe Group 0 High PCIe09_RX+ A Server Module may map up to 8 higher bandwidth PCIe09_RX- PCIe lanes to Group 0 High PCIe10_RX+ PCIe10_RX- PCIe11_RX+ PCIe11_RX- PCIe12_RX+ PCIe12_RX- PCIe13_RX+ PCIe13_RX- PCIe14_RX+ Page 37 Copyright © 2024 ADLINK Technology, Inc.
  • Page 38 PCIe25_TX- PCIe26_TX+ PCIe26_TX- PCIe27_TX+ PCIe27_TX- PCIe28_TX+ PCIe28_TX- PCIe29_TX+ PCIe29_TX- PCIe30_TX+ PCIe30_TX- PCIe31_TX+ PCIe31_TX- PCIe16_RX+ PCI Express Differential Receive Pairs 16-31 I PCIe AC coupled off Module PCIe16_RX- PCIe Group 1 PCIe17_RX+ PCIe17_RX- Page 38 Copyright © 2024 ADLINK Technology, Inc.
  • Page 39 PCIe29_RX+ PCIe29_RX- PCIe30_RX+ PCIe30_RX- PCIe31_RX+ PCIe31_RX- PCIe32_TX+ PCI Express Differential Transmit Pairs 32-47 O PCIe AC coupled on Module PCIe32_TX- PCIe Group 2 PCIe33_TX+ PCIe33_TX- PCIe34_TX+ PCIe34_TX- PCIe35_TX+ PCIe35_TX- PCIe36_TX+ PCIe36_TX- PCIe37_TX+ Page 39 Copyright © 2024 ADLINK Technology, Inc.
  • Page 40 PCI Express Differential Receive Pairs 32-47 I PCIe AC coupled off Module PCIe32_RX- PCIe Group 2 PCIe33_RX+ PCIe33_RX- PCIe34_RX+ PCIe34_RX- PCIe35_RX+ PCIe35_RX- PCIe36_RX+ PCIe36_RX- PCIe37_RX+ PCIe37_RX- PCIe38_RX+ PCIe38_RX- PCIe39_RX+ PCIe39_RX- PCIe40_RX+ PCIe lane 40-47 not supported PCIe40_RX- Page 40 Copyright © 2024 ADLINK Technology, Inc.
  • Page 41 PCIe reference clock request signals from Carrier I/O OD PD 1K devices for PCIe_REFCLK1 clock pair 3.3V 3.3V PCIe_CLKREQ0_2# PCIe reference clock request signals from Carrier I/O OD PD 1K devices for PCIe_REFCLK2 clock pair 3.3V Page 41 Copyright © 2024 ADLINK Technology, Inc.

  • Page 42: Usb

    USB 1.1/2.0 compliant USB4- 3.3VSB USB5+ USB0 may be configured as a USB client or as a host, USB Client mode – Not supported USB5- or both at the Module designer's discretion. All other Page 42 Copyright © 2024 ADLINK Technology, Inc.
  • Page 43 USB2_SSTX1+ USB2_SSTX1- These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB0_SSxxx+/- USB3_SSTX1+ shall be used with the USB0 USB 2.0 pair and so on, Page 43 Copyright © 2024 ADLINK Technology, Inc.
  • Page 44 RSMRST_OUT# is also described in Power and System Management section Note: 4x USB3.2 Gen2x4 required BIOS modification by project basis. In addition, this platform does not support USB4 feature, thus, additional signals required by USB4 are not shown here. Page 44 Copyright © 2024 ADLINK Technology, Inc.

  • Page 45: Port 80 Support On Usb_Pd_I2C

    Delivery Controller slave. USB_PD_I2C_CLK I2C clock line between Module based Embedded 3.3VSB This pin is used for Port 80 display at this product Controller master and Carrier based USB Power (TBC) Delivery Controller slave. Page 45 Copyright © 2024 ADLINK Technology, Inc.

  • Page 46: Sata

    UART 0, 1_CTS#, RTS# only available if routed from PCH and UART1_RTS# signal, active low by project basis UART0_CTS# Logic level asynchronous serial port Clear to Send I 3.3V UART1_CTS# input, active low Page 46 Copyright © 2024 ADLINK Technology, Inc.

  • Page 47: I2C

    GP_SPI device (“Master Out Slave In”) GP_SPI_CLK Clock from the Module to Carrier GP_SPI device O 3.3V By project basis discussion GP_SPI_CS0# GP_SPI chip selects, active low O 3.3V By project basis discussion GP_SPI_CS1# GP_SPI_CS2# GP_SPI_CS3# Page 47 Copyright © 2024 ADLINK Technology, Inc.

  • Page 48: Smbus

    3.3V GPIO_02 inputs. GPIO_03 GPIO_04 As inputs, these pins should be able to generate an GPIO_05 interrupt to the Module host. GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 Page 48 Copyright © 2024 ADLINK Technology, Inc.

  • Page 49: Thermal Protection

    CMOS eSPI_IO2 between master and slaves. 1.8VSB eSPI_IO3 eSPI_CS0# eSPI Master Chip Select Outputs. A low selects a PU 10K eSPI_CS1# particular eSPI slave for the transaction. Each of the COMS 1.8VSB Page 49 Copyright © 2024 ADLINK Technology, Inc.

  • Page 50: Boot Spi (Bios Only) And Boot Select

    Clock support is 50MHz, can be adjusted by project basis VCC_BOOT_SPI VCC_BOOT_SPI Power supply for Carrier Board SPI – sourced from O 3.3VSB Module – nominally either 1.8V or 3.3V. The Module shall provide a minimum of 100mA on Page 50 Copyright © 2024 ADLINK Technology, Inc.

  • Page 51: Power & System Management

    Indicates system is in Suspend to RAM state. Active low output. An O 3.3VSB inverted copy of SUS_S3# on the Carrier Board should be used to enable the non-standby power on a typical ATX supply. Page 51 Copyright © 2024 ADLINK Technology, Inc.

  • Page 52: Rapid Shutdown

    Trigger for Rapid Shutdown. Must be driven to 5V I 5VSB Not supported though a <=50 ohm source impedance for ≥ 20 μs. Pull-down / disable on Module if RAPID_SHUTDOWN pin is not asserted. Page 52 Copyright © 2024 ADLINK Technology, Inc.

  • Page 53: Module Type Definition

    VCC to the COM-HPC Module) if an incompatible Module pin-out type is detected. All three TYPE[x] pins should be monitored by the Carrier. The Carrier Board logic may also implement a fault indicator such as an LED. Page 53 Copyright © 2024 ADLINK Technology, Inc.

  • Page 54: Miscellaneous Signals

    3.3V 3.3V RSVD Reserved pins. These may be assigned functions in future versions of this specification. Reserved pins shall not be connected to anything, and shall not be connected to each other. Page 54 Copyright © 2024 ADLINK Technology, Inc.

  • Page 55: Power And Ground

    Real-time clock circuit-power input. Nominally +3.0V. Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to Carrier Board GND plane(s). Page 55 Copyright © 2024 ADLINK Technology, Inc.

  • Page 56: Additional Features

    This chapter describes the connectors, LEDs, and switches located on the module and are not necessarily included in the PICMG standard specification. The locations of these parts are shown below: Module Fan Connector BIOS Default 40-pin Reset Debug Connector Figure 3 – Module feature locations (front) Page 56 Copyright © 2024 ADLINK Technology, Inc.

  • Page 57: Figure 4 - Module Feature Locations (Back)

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 J2 connector J1 connector Figure 4 – Module feature locations (back) Page 57 Copyright © 2024 ADLINK Technology, Inc.

  • Page 58: Debug Connector (40-Pin Connector)

    This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module: Test points for measurement of internal power rails SPI BIOS programming interface I2C bus for BIOS POST code readout Module EC and MMC programming interface Page 58 Copyright © 2024 ADLINK Technology, Inc.

  • Page 59: Status Leds

    Rebooted by power button WD LED = LED OFF Rebooted by reset button WD LED = LED OFF Note: only a Reset not initiated by the BMC can clear the WD LED (user action) Page 59 Copyright © 2024 ADLINK Technology, Inc.

  • Page 60: Exception Codes

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 5.3 Exception Codes Exception Code Error Message NOERROR NO_SLP_S5 NO_SLP_S4 NO_SLP_S3 BIOS_FAIL RESET_FAIL NO_CB_PWROK CRITICAL_TEMP POWER_FAIL VOLTAGE_FAIL RSMRST_FAIL NO_VDDQ_PG NO_VCORE_PG NO_SYS_GD NO_V3P3A NO_PWRSRC_GD NO_PCH_PG Page 60 Copyright © 2024 ADLINK Technology, Inc.

  • Page 61: Fan Connector

    PICMG COM-HPC R1.1 5.4 Fan Connector Connector Type: JVE 24W1125A-04M00 Name Description FAN_PWMOUT FAN_TACHIN 12V* The supply voltage and maximum current of the fan connector is dependent on the module’s input voltage (VCC_12V pins). Page 61 Copyright © 2024 ADLINK Technology, Inc.

  • Page 62: Bios Default Reset

    Press and hold the BIOS Setup Default Reset Button and boot up the system. Release the button when the BIOS prompt screen appears. Once BIOS settings are reset to default, you will be asked to reboot the system. Page 62 Copyright © 2024 ADLINK Technology, Inc.

  • Page 63: Bios Boot Select

    In either mode, BIOS Select and Mode Configuration Switch, Pin 1 is used to select whether to boot from SPI0 or SPI1. Mode Pin 1 Pin 2 Boot from SPI0 (default) Boot from SPI1 Set BIOS to PICMG mode (default) Set BIOS to Failsafe BIOS mode Page 63 Copyright © 2024 ADLINK Technology, Inc.

  • Page 64: System Resources

    Intel® Serial IO I2C Host Controller – 7AFD 7FFFEF2000-7FFFEF2FFF Intel® Serial IO UART Host Controller – 7AA8 7FFFEC0000-7FFFEDFFFF Intel® Innovation Platform Framework Processor Participant 4000000000-400FFFFFFF Intel® UHD Graphics 770 FED20000-FED7FFFF Motherboard resource FED45000-FED8FFFF FED90000-FED93FFF FEDA0000-FEDA0FFF FEDA1000-FEDA1FFF FEDC0000-FEDC7FFF Page 64 Copyright © 2024 ADLINK Technology, Inc.
  • Page 65 PCI Express Root Complex 000F0000-000FFFFF PCI Express Root Complex 000EC000-000EFFFF PCI Express Root Complex 000E8000-000EBFFF PCI Express Root Complex 000E4000-000E7FFF PCI Express Root Complex 000E0000-000E3FFF PCI Express Root Complex 000A0000-000BFFFF PCI Express Root Complex Page 65 Copyright © 2024 ADLINK Technology, Inc.

  • Page 66: I/O Map

    4D0h - 4D1h Programmable interrupt controller 680h - 69Fh Motherboard resources A00h - A1Fh, A20h – A2Fh, A30h - A3Fh, A40h - Motherboard resources A4Fh, A50h - A5Fh and A60h - A6Fh Page 66 Copyright © 2024 ADLINK Technology, Inc.

  • Page 67: Interrupt Request (Irq) Lines

    Serial Port 1 Serial Port 3 Serial Port 4 Intel® Serial IO GPIO Host Controller – INT1056 Intel® Serial IO UART Host Controller High Definition Audio Controller Intel® Active Management Technology – SOL Page 67 Copyright © 2024 ADLINK Technology, Inc.

  • Page 68: Pci Configuration Space Map

    Internal Intel Data acquisition/signal process Internal Intel USB3.0 XHCI Internal Intel RAM Internal Intel Serial Bus controller Internal Intel Serial Bus controller Internal Intel Serial Bus controller Internal Intel Serial Bus controller Page 68 Copyright © 2024 ADLINK Technology, Inc.
  • Page 69 Intel Communication device Internal Intel Serial Bus controller Internal Intel ISA bridge Internal Intel Audio device Internal Intel SMBUS Internal Intel Serial Bus controller Internal Intel Ethernet controller(PCI Express) Internal Intel Ethernet controller(PCI Express) Page 69 Copyright © 2024 ADLINK Technology, Inc.

  • Page 70: Pci Interrupt Routing Map

    Port 2 Port 3 Port 4 Port 5 Int0 INTB:17 INTB:17 INTC:18 INTD:19 INTA:16 Int1 INTC:18 INTC:18 INTD:19 INTA:16 INTB:17 Int2 INTD:19 INTD:19 INTA:16 INTB:17 INTC:18 Int3 INTA:16 INTA:16 INTB:17 INTC:18 INTD:19 Page 70 Copyright © 2024 ADLINK Technology, Inc.

  • Page 71: Smbus Address Table

    PICMG COM-HPC R1.1 6.6 SMBus Address Table Device Address DDR5 Channel A(SO-DIMM1) DDR5 Channel B(SO-DIMM2) DDR5 Channel C(SO-DIMM3) DDR5 Channel D(SO-DIMM4) 6.7 I2C Address Table Device Address Thermal Sensor Thermal Sensor EEPROM Crypto Authentication Page 71 Copyright © 2024 ADLINK Technology, Inc.

  • Page 72: Bios Configurations

    Thermal Management ► System Time Watchdog Timer ► Super IO Configuration ► Miscellaneous ► Network Stack Configuration ► Trusted Computing ► Boot Save & Exit Boot Save Options Configuration Default Options Boot Override Page 72 Copyright © 2024 ADLINK Technology, Inc.

  • Page 73: Main

    Display CPU Signature. CPU Brand String Info only Display CPU Brand Name. CPU Frequency Info only Display CPU Frequency Total Memory Info only Display installed memory size. Memory Frequency Info only Display memory frequency. Page 73 Copyright © 2024 ADLINK Technology, Inc.

  • Page 74: Board Information

    The Boot counter is increased after a HW- or SW-Reset or after a successful power-up. Boot Reason Read only The boot reason is the event which causes the reboot of the system. Page 74 Copyright © 2024 ADLINK Technology, Inc.

  • Page 75: System Date And Time

    Graphics Configuration submenu Power Management submenu System Management submenu Thermal Management submenu Watchdog Timer submenu USB Configuration submenu AMT Configuration submenu AMI Graphic Output Protocol Policy submenu Super IO Configuration submenu Page 75 Copyright © 2024 ADLINK Technology, Inc.

  • Page 76: Cpu Configuration

    Boot Guard ACM Policy Status value C6DRAM Disabled Enable/Disable moving of DRAM contents to PRM memory when CPU is in C6 state Enable CPU Flex Ratio Override Disabled Enable/Disable CPU Flex Ratio Programming Enable Page 76 Copyright © 2024 ADLINK Technology, Inc.
  • Page 77 {0,0}, Pcode will enable all cores. Active Efficient-cores Number of E-cores to enable in each processor package. Note: Number of Cores and E-cores are looked at together. When both are {0,0}, Pcode will enable all cores. Page 77 Copyright © 2024 ADLINK Technology, Inc.
  • Page 78 DPR Memory Size (MB) Reserve DPR memory size (0-255) MB Reset AUX Content Reset TPM Aux content. Txt may not functional after AUX content gets reset. CPU SMM Enhancement submenu CPU SMM Enhancement Page 78 Copyright © 2024 ADLINK Technology, Inc.
  • Page 79 Info only L3 Cache Info only 7.3.1.2 CPU Configuration > Performance-core Information Feature Options Description L1 Data Cache Info only L1 Instruction Cache Info only L2 Cache Info only L3 Cache Info only Page 79 Copyright © 2024 ADLINK Technology, Inc.

  • Page 80: Power & Performance

    Disabled Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20) Enabled Page 80 Copyright © 2024 ADLINK Technology, Inc.
  • Page 81 Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit Enable C states Disabled Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized. Enable Thermal Monitor Disabled Enable/Disable Thermal Monitor Enabled Page 81 Copyright © 2024 ADLINK Technology, Inc.
  • Page 82 Package Power Limit MSR Lock Disabled Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register. Enable Page 82 Copyright © 2024 ADLINK Technology, Inc.
  • Page 83 Min Voltage Override. Enable to override minimum voltage for runtime and for C8. Enable VccIn Aux Icc Max Sets the Max Icc VccIn Aux value defined in 1/4A increments. Range is 0-512. For an IccMax 32A, enter 128(32*4). Page 83 Copyright © 2024 ADLINK Technology, Inc.
  • Page 84 ADL S 681 35W ADL S 801 35W ADL S 801 65W ADL S 401 35W ADL S 401 65W ADL S 601 35W ADL S 601 65W ADL S 201 35W Page 84 Copyright © 2024 ADLINK Technology, Inc.
  • Page 85 RPL S 641 125W RPL S 801 80W RPL S 801 95W RPL S 641 35W RPL HX SBGA 8161 55W RPL HX SBGA 8121 55W RPL HX SBGA 881 55 RPL HX Page 85 Copyright © 2024 ADLINK Technology, Inc.
  • Page 86 Configure Acoustic Noise Settings for IA, GT and SA domains Core/IA VR Settings submenu Configure Core/IA VR Settings GT VR Settings submenu Configure GT VR Settings RFI Settings submenu Configure RFI Settings Page 86 Copyright © 2024 ADLINK Technology, Inc.
  • Page 87 Set VR GT Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled Fast/4 Fast/8 Fast/16 Page 87 Copyright © 2024 ADLINK Technology, Inc.
  • Page 88 PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3. PS3 Enable Disabled PS3 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3. Enable Page 88 Copyright © 2024 ADLINK Technology, Inc.
  • Page 89 VR TDC Time Window, value in seconds. 1s is default. Range from 1s to 448s. 2 sec 3 sec 4 sec 5 sec 6 sec 7 sec 8 sec 10 sec 12 sec 14 sec 16 sec 20 sec 24 sec Page 89 Copyright © 2024 ADLINK Technology, Inc.
  • Page 90 7.3.2.1.2.3 Power & Performance > CPU - Power Management Control > CPU VR Settings > GT VR Settings Feature Options Description VR Config Enable Disabled VR Config Enable Enable Current AC Loadline Current AC Loadline Current DC Loadline Current DC Loadline Page 90 Copyright © 2024 ADLINK Technology, Inc.
  • Page 91 IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4. IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command IMON Offset 0x4. Page 91 Copyright © 2024 ADLINK Technology, Inc.
  • Page 92 5 sec 6 sec 7 sec 8 sec 10 sec 12 sec 14 sec 16 sec 20 sec 24 sec 28 sec 32 sec 40 sec 48 sec 56 sec 64 sec Page 92 Copyright © 2024 ADLINK Technology, Inc.
  • Page 93 Set desired RFI frequency, in increments of 100KHz. (For a frequency of 100.6MHz, enter 1006.) FIVR Spread Spectrum Disabled Enable or Disable the FIVR Spread Spectrum Enable RFI Spread Spectrum 0.5% Set the Spread Spectrum 1.5% Page 93 Copyright © 2024 ADLINK Technology, Inc.
  • Page 94 Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR Enable 7.3.2.2 Power & Performance > GT - Power Management Control Feature Options Description RC6(Render Standby) Disabled Check to enable render standby support. Enable Page 94 Copyright © 2024 ADLINK Technology, Inc.
  • Page 95 500Mhz 550Mhz 600Mhz 650Mhz 700Mhz 750Mhz 800Mhz 850Mhz 900Mhz 950Mhz 1000Mhz 1050Mhz 1100Mhz 1150Mhz 1200Mhz Disable Turbo GT frequency Disabled Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited Enable Page 95 Copyright © 2024 ADLINK Technology, Inc.

  • Page 96: Intel(R) Time Coordinated Computing

    Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized. Intel(R) Speed Shift Technology submenu Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware Page 96 Copyright © 2024 ADLINK Technology, Inc.
  • Page 97 Intel(R) TCC Authentication determines the key to be used. OEM Enrolled Key is built in by OEM. Non-OEM Intel(R) TCC Authentication Disabled Enrolled Key can be add by user. Non-OEM Enrolled Key OEM Enrolled Key Page 97 Copyright © 2024 ADLINK Technology, Inc.

  • Page 98: Graphics Configuration

    > 2048MB aperture. To use this feature, please disable CSM Support. 256MB 512MB 1024MB DVMT Pre-Allocated Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. 128M 160M Page 98 Copyright © 2024 ADLINK Technology, Inc.
  • Page 99 Cdynmax Clamping Enable Disabled Enable/Disable Cdynmax Clamping Enabled Cd Clock Frequency 192 Mhz Select the highest Cd Clock frequency supported by the platform 307.2 Mhz 326.4 Mhz 556.8 Mhz 652.8 Mhz Max CdClock freq Page 99 Copyright © 2024 ADLINK Technology, Inc.
  • Page 100 EFP3 EFP2 EFP4 LCD Panel Type VBIOS Default Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. 640x480 LVDS 800x600 LVDS 1024x768 LVDS 1280x1024 LVDS Page 100 Copyright © 2024 ADLINK Technology, Inc.
  • Page 101 Int-DisplayPort encoder from Port-A.\neDP Port-D:LFP Driven by Int-DisplayPort encoder from Port-D(through PCH). Panel Color Depth 18 Bit Select the LFP Panel Color Depth 24 Bit Backlight Brightness Set VBIOS Brightness.\nRange : 0-255. Page 101 Copyright © 2024 ADLINK Technology, Inc.

  • Page 102: Power Management

    Info only has effect, if the module is in ATX-Mode. Power Consumption Submenu 7.3.5.1 Power Management > Power Consumption Feature Options Description Power Consumption Info only Main Current Read only Display input current. Page 102 Copyright © 2024 ADLINK Technology, Inc.

  • Page 103: System Management

    Uptime & Power Cycles Counter Read only System Restart Event Read only 4096 Bytes User-Flash Read only Runtime Watchdog Read only Temperatures Read only Voltage Monitor Read only Display Backlight Control Read only Page 103 Copyright © 2024 ADLINK Technology, Inc.
  • Page 104 Read only I2C Bus 3 Read only Other BMC Read only Error Log Read only Wake-by-BMC Read only Soft Fan Read only Parameter Memory Read only Ext-GPIO Input Interrupt Support Read only Page 104 Copyright © 2024 ADLINK Technology, Inc.

  • Page 105: Thermal Management

    This value is the temperature threshold of the active cooling trip point. 40 C 50 C 60 C 70 C Refer to BMC Watchdog ACPI Event Shutdown Disabled Watchdog ACPI Event Shutdown Enabled/Disabled Enabled Temperatures and Fan Speed Info only Page 105 Copyright © 2024 ADLINK Technology, Inc.
  • Page 106 CPU Smart Fan Temperature Source CPU Sensor CPU Smart Fan Temperature Source. Board Sensor CPU Fan Mode AUTO CPU Fan Mode Fan Off Fan On Trigger Point 1 Info only Trigger Temperature Trigger Temperature Page 106 Copyright © 2024 ADLINK Technology, Inc.

  • Page 107: Watchdog Timer

    ATTENTION: Pressing F12 during start up disables Info only the Power Up Watchdog. RunTime Watchdog Disabled The RunTime Watchdog resets the system after a certain amount of time after power up. Enabled Page 107 Copyright © 2024 ADLINK Technology, Inc.

  • Page 108: Usb Configuration

    100 ms, for a Hub port the delay is taken from Hub descriptor. Manual 7.3.10 AMT Configuration Feature Options Description USB Provisioning of AMT Disabled Enable/Disable of AMT USB Provisioning. Enabled MAC Pass Through Disabled Enable/Disable MAC Pass Through function. Enabled Page 108 Copyright © 2024 ADLINK Technology, Inc.
  • Page 109 Change Secure Erase module behavior:\nSimulated: Performs SE flow without erasing SSD\nReal: Erase SSD.\n*** If SATA device is used, OEM could use SECURE_ERASE_HOOK_PROTOCOL to remove SATA power to skip G3 cycle. *** Real Page 109 Copyright © 2024 ADLINK Technology, Inc.

  • Page 110: Ami Graphic Output Protocol Policy

    Enabled 7.3.11 AMI Graphic Output Protocol Policy Feature Options Description Output Select Info only Output Interface 7.3.12 Super IO Configuration Feature Options Super IO Configuration Info only ITE5121 Super IO Configuration submenu Page 110 Copyright © 2024 ADLINK Technology, Inc.
  • Page 111 Enable or Disable Serial Port (COM). Disabled IO=3F8h; IRQ=4 Device Settings Fixed configuration of serial port. Auto Change Settings Select an optimal setting for Super IO device. IO=3F8h; IRQ=4 IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12 Page 111 Copyright © 2024 ADLINK Technology, Inc.
  • Page 112 Change Settings Select an optimal setting for Super IO device. IO=2F8h; IRQ=3 IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12 Change Settings Normal Select an optimal settings for Super IO Device. High Speed Page 112 Copyright © 2024 ADLINK Technology, Inc.
  • Page 113 Auto Change Settings Select an optimal setting for Super IO device. IO=240h; IRQ=5 IO=248h; IRQ=3,4,5,6,7,9,10,11,12 IO=250h; IRQ=3,4,5,6,7,9,10,11,12 IO=258h; IRQ=3,4,5,6,7,9,10,11,12 Change Settings Normal Select an optimal settings for Super IO Device. High Speed Page 113 Copyright © 2024 ADLINK Technology, Inc.

  • Page 114: Serial Console Redirection

    Select an optimal settings for Super IO Device. High Speed 7.3.13 Serial Console Redirection Feature Options Description Serial Port Console Info only COM0 Info only Console Redirection Enabled Console Redirection Enable or Disable. Disabled Console Redirection Settings Submenu Page 114 Copyright © 2024 ADLINK Technology, Inc.
  • Page 115 Console Redirection Settings Submenu Serial Port for Out-of-Band Info only Management/ Windows Emergency Management Info only Services (EMS) Console Redirection EMS Enabled Console Redirection Enable or Disable. Disabled Console Redirection Settings Submenu Page 115 Copyright © 2024 ADLINK Technology, Inc.
  • Page 116 VT-UTF8 Combo Key Support Disabled Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals. Enable Recorder Mode Disabled With this mode enabled only text will be sent. This is to capture Terminal data. Page 116 Copyright © 2024 ADLINK Technology, Inc.
  • Page 117 115200 Data Bits Data Bits. Parity None A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's Page 117 Copyright © 2024 ADLINK Technology, Inc.
  • Page 118 Putty KeyPad VT100 Select FunctionKey and KeyPad on Putty. LINUX XTERMR6 ESCN VT400 7.3.13.3 Serial Console Redirection > Console Redirection Settings (COM2) Feature Options Description COM2 Info only Console Redirection Settings Info only Page 118 Copyright © 2024 ADLINK Technology, Inc.
  • Page 119 With this mode enabled only text will be sent. This is to capture Terminal data. Enable Resolution 100x31 Disabled Enables or disables extended terminal resolution Enable Putty KeyPad VT100 Select FunctionKey and KeyPad on Putty. Page 119 Copyright © 2024 ADLINK Technology, Inc.
  • Page 120 Parity bit is always 0. Mark and Space Parity do not allow for error detection.. Mark Space Stop Bits Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 Page 120 Copyright © 2024 ADLINK Technology, Inc.
  • Page 121 VT100. See above, in Console Redirection Settings page, for more Help with Terminal Type/Emulation. VT100+ VT-UTF8 ANSI Bits per second 9600 Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds. 19200 Page 121 Copyright © 2024 ADLINK Technology, Inc.

  • Page 122: Miscellaneous

    From EC SMBUS Select Configuration from PCH or EC. From PCH WOL From S5 This Config to control power on/off LAN in S5 State by SEMA(EC). LID Function Disabled Enable/Disable LID Function Enabled Page 122 Copyright © 2024 ADLINK Technology, Inc.

  • Page 123: Network Stack Configuration

    Use either +/- or numeric keys to set the value. Media detect count Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value. Page 123 Copyright © 2024 ADLINK Technology, Inc.

  • Page 124: Pci Subsystem Settings

    Enable or Disable SM3_256 PCR Bank Enabled Pending operation None Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device. TPM Clear Page 124 Copyright © 2024 ADLINK Technology, Inc.

  • Page 125: Ptt Configuration

    TPM Device Selection dTPM Selects TPM device: PTT or discrete TPM.\nPTT - enables PTT in SkuMgr\ndTPM - disables PTT is SkuMgr\n\nWarning!\nPTT/dTPM will be disabled and all data saved on it will be lost. Page 125 Copyright © 2024 ADLINK Technology, Inc.

  • Page 126: Chipset

    Enabled DMA Control Guarantee Disabled Enable/Disable DMA_CONTROL_GUARANTEE bit Enabled Above 4GB MMIO BIOS assignment Disabled Enable/Disable above 4GB MemoryMappedIO BIOS assignment\n\nThis is enabled automatically when Aperture Size is set to 2048MB. Enabled Page 126 Copyright © 2024 ADLINK Technology, Inc.
  • Page 127 MC1 Ch0 DIMM 0 Info only Size Number of Ranks Manufacturer MC 1 Ch0 DIMM 1 Memory Test on Warm Boot Disabled Enable Or Disable Base Memory Test Run on Warm Boot Enabled Page 127 Copyright © 2024 ADLINK Technology, Inc.
  • Page 128 Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller 1 GB 1.25 GB 1.5 GB 1.75 GB 2 GB 2.25 GB 2.5 GB 2.75 GB 3 GB 3.25 GB 3.5 GB Page 128 Copyright © 2024 ADLINK Technology, Inc.
  • Page 129 PCH PCI External Gfx Card Primary Display Configuration submenu External Gfx Card Primary Display Configuration Internal Graphics Disabled Keep IGFX enabled based on the setup options. Enabled GTT Size Select the GTT Size Page 129 Copyright © 2024 ADLINK Technology, Inc.
  • Page 130 128M 160M 32M/F7 DVMT Total Gfx Mem 128M Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device. 256M Intel Graphics Pei Display Peim Disabled Enable/Disable Pei (Early) Display Enabled Page 130 Copyright © 2024 ADLINK Technology, Inc.
  • Page 131 Enabled PCI Express Slot Selection Select the PCIe M2 or CEMx4 slot CEMx4 slot PCI Express Root Port 1 Submenu PCI Express Root Port 2 Submenu PCI Express Root Port 3 submenu Page 131 Copyright © 2024 ADLINK Technology, Inc.
  • Page 132 Gen4 Eq Phase3 Method Hardware PCIe Gen4 Equalization Phase 3 Method Static Coeff. Disabled Enable/Disable Access Control Services Extended Capability Enabled Disabled Enable/Disable Precision Time Measurement Enabled Disabled Enable/Disable Downstream Port Containment Enabled Page 132 Copyright © 2024 ADLINK Technology, Inc.
  • Page 133 Disabled Root PCI Express System Error on Non-Fatal Error Enable/Disable. Enabled SECE Disabled Root PCI Express System Error on Correctable Error Enable/Disable. Enabled PME SCI Disabled PCI Express PME SCI Enable/Disable. Enabled Page 133 Copyright © 2024 ADLINK Technology, Inc.
  • Page 134 Disabled: LTR override values will not be forced. Enable: LTR override values will be forced and LTR messages from the device will be ignored. LTR Lock Disabled PCIE LTR Configuration Lock Enabled Page 134 Copyright © 2024 ADLINK Technology, Inc.
  • Page 135 PCI Express L1 Substates settings. Enabled Gen3 Eq Phase3 Method Hardware PCIe Gen3 Equalization Phase 3 Method Static Coeff. Gen4 Eq Phase3 Method Hardware PCIe Gen4 Equalization Phase 3 Method Static Coeff. Page 135 Copyright © 2024 ADLINK Technology, Inc.
  • Page 136 PCI Express Device Non-Fatal Error Reporting Enable/Disable. Enabled Disabled PCI Express Device Correctable Error Reporting Enable/Disable. Enabled Disabled PCI Express Completion Timer TO Enable/Disable. Enabled SEFE Disabled Root PCI Express System Error on Fatal Error Enable/Disable. Enabled Page 136 Copyright © 2024 ADLINK Technology, Inc.
  • Page 137 SA PCIE Latency Reporting Enable/Disable Enabled Snoop Latency Override Disabled Snoop Latency Override for SA PCIE. Disabled: Disable override. Manual Manual: Manually enter override values. Auto Auto (default): Maintain default BIOS flow. Page 137 Copyright © 2024 ADLINK Technology, Inc.
  • Page 138 Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set. Slot PCI Express Clock Gating Disabled PCI Express Clock Gating Enable/Disable for each root port. Enabled Page 138 Copyright © 2024 ADLINK Technology, Inc.
  • Page 139 Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS Gen3 Gen4 Gen3/Gen4 Gen5 Multi-VC Disabled Enable/Disable Multi Virtual Channel Enabled EDPC Disabled Enable/Disable Rootport extensions for Downstream Port Containment Enabled Disabled PCI Express Unsupported Request Reporting Enable/Disable. Enabled Page 139 Copyright © 2024 ADLINK Technology, Inc.
  • Page 140 Advanced Error Reporting Enable/Disable. Enabled PCIe Speed Auto Configure PCIe Speed Gen1 Gen2 Gen3 Gen4 Enable ClockReq Messaging Disabled Enable or Disable ClockReq Messaging Enabled Transmitter Half Swing Disabled Transmitter Half Swing Enable/Disable. Enabled Page 140 Copyright © 2024 ADLINK Technology, Inc.
  • Page 141 CPU PCIe Gen4 HWEQ Config Info only UPTP Upstream Port Transmitter Preset DPTP Downstream Port Transmitter Preset CPU PCIe Gen5 HWEQ Config Info only UPTP Upstream Port Transmitter Preset DPTP Downstream Port Transmitter Preset Page 141 Copyright © 2024 ADLINK Technology, Inc.

  • Page 142: Chipset > Pch-Io Configuration

    ACPI WDAT table will not be published. Enabled Pcie Pll SSC Auto Pcie Pll SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%. 0.0% 0.1% 0.2% 0.3% 0.4% 0.5% 0.6% 0.7% 0.8% 0.9% 1.0% 1.1% Page 142 Copyright © 2024 ADLINK Technology, Inc.
  • Page 143 PCI Express Port8xh Decode Enable/Disable. Enabled PCH PCIE Clock Gating Disabled PCH PCI Express Clock Gating Enable/Disable for all port Enabled PCH PCIE Power Gating Disabled PCH PCI Express Power Gating Enable/Disable for all port Enabled Page 143 Copyright © 2024 ADLINK Technology, Inc.
  • Page 144 PCI Express Root Port 6 submenu PCI Express Root Port Settings. PCI Express Root Port 7 submenu PCI Express Root Port Settings. PCI Express Root Port 8 submenu PCI Express Root Port Settings. Page 144 Copyright © 2024 ADLINK Technology, Inc.
  • Page 145 Set the ASPM Level: Force L0 - Force all links to L0 State : AUTO - BIOS auto configure : DISABLE - Disables ASPM Enabled L1 Substates Disabled PCI Express L1 Substates settings. Enabled Page 145 Copyright © 2024 ADLINK Technology, Inc.
  • Page 146 Root PCI Express System Error on Non-Fatal Error Enable/Disable. Enabled SECE Disabled Root PCI Express System Error on Correctable Error Enable/Disable. Enabled PME SCI Disabled PCI Express PME SCI Enable/Disable. Enabled Hot Plug Disabled PCI Express Hot Plug Enable/Disable. Enabled Page 146 Copyright © 2024 ADLINK Technology, Inc.
  • Page 147 Non Snoop Latency Override for PCH PCIE.Disabled: Disable override. Manual Manual: Manually enter override values. Auto Auto (default): Maintain default BIOS flow. LTR Lock Disabled PCIE LTR Configuration Lock Enabled Peer Memory Write Enable Disabled Peer Memory Write Enable/Disable Enabled Page 147 Copyright © 2024 ADLINK Technology, Inc.
  • Page 148 Otherwise all drives spin up at boot. Enabled SATA Device Type Hard Disk Drive Identify the SATA port is connected to Solid State Drive or Hard Disk Drive Solid State Drive Page 148 Copyright © 2024 ADLINK Technology, Inc.
  • Page 149 Otherwise all drives spin up at boot. Enabled SATA Device Type Hard Disk Drive Identify the SATA port is connected to Solid State Drive or Hard Disk Drive Solid State Drive Page 149 Copyright © 2024 ADLINK Technology, Inc.
  • Page 150 Enable/Disable HSII feature. It may lead to increased power consumption. Enabled USB3.1 Portx Speed Selection Port Selection value in decimal for Gen1; Default - Gen2; Bit 0 corresponds to Port 0 and so on Page 150 Copyright © 2024 ADLINK Technology, Inc.
  • Page 151 The following devices depend on each other:I2C0 and I2C1,2,3 UART0 and UART1,SPI0,1 UART2 and I2C4,5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0)UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC) Page 151 Copyright © 2024 ADLINK Technology, Inc.
  • Page 152 UART2 and I2C4,5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0)UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC) GPIO IRQ Route IRQ14 Route all GPIOs to one of the IRQ. IRQ15 Page 152 Copyright © 2024 ADLINK Technology, Inc.

  • Page 153: Security

    Force System to User Mode. Install factory default Secure Boot key databases Reset To Setup Mode Info only Key Management Enables expert users to modify Secure Boot Policy variables without full authentication Page 153 Copyright © 2024 ADLINK Technology, Inc.

  • Page 154: Boot

    If Disabled, PS2 devices will be skipped. Enabled NetWork Stack Driver Support Disabled Link If Disabled, NetWork Stack Driver will be skipped. Enabled Redirection Support Disabled If disable, Redirection function will be disabled. Enabled Page 154 Copyright © 2024 ADLINK Technology, Inc.

  • Page 155: Save & Exit

    Restore/Load Default values for all the setup options. Save as User Defaults Save the changes done so far as User Defaults. Restore User Defaults Restore the User Defaults to all the setup options. Page 155 Copyright © 2024 ADLINK Technology, Inc.

  • Page 156: Bios Checkpoints, Beep Codes

    These PCI add-on cards show the value of I/O port 80h on an LED display. Aptio V Checkpoint and Beep Codes You can download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes Page 156 Copyright © 2024 ADLINK Technology, Inc.

  • Page 157: Status Code Ranges

    0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI) 8.2 Standard Status Codes 8.2.1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on. Reset type detection (soft/hard). Page 157 Copyright © 2024 ADLINK Technology, Inc.

  • Page 158: Pei Phase

    Microcode not found 0x0F Microcode not loaded 8.2.2 PEI Phase Status Code Description Progress Codes 0x10 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 – 0x14 Reserved for CPU Page 158 Copyright © 2024 ADLINK Technology, Inc.
  • Page 159 Post-Memory North Bridge initialization is started 0x38 – 0x3A Reserved for North Bridge initialization 0x3B Post-Memory South Bridge initialization is started 0x3C -0x3E Reserved for South Bridge 0x3F-0x4E OEM post memory initialization codes Page 159 Copyright © 2024 ADLINK Technology, Inc.
  • Page 160 S3 Resume is stared (S3 Resume PPI is called by the DXE IPL) 0xE1 S3 Boot Script execution 0xE2 Video repost 0xE3 OS S3 wake vector call 0xE4-0xE7 Reserved for future AMI progress codes Page 160 Copyright © 2024 ADLINK Technology, Inc.
  • Page 161 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB – 0xFF Reserved for future AMI error codes Page 161 Copyright © 2024 ADLINK Technology, Inc.

  • Page 162: Dxe Status Codes

    PCI host bridge initialization 0x69 North Bridge DXE initialization is started 0x6A North Bridge DXE SMM initialization is started 0x6B – 0x6F Reserved for North Bridge DXE initialization (North Bridge module specific) Page 162 Copyright © 2024 ADLINK Technology, Inc.
  • Page 163 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initialization 0x9A USB initialization is started 0x9B USB Reset 0x9C USB Detect 0x9D USB Enable Page 163 Copyright © 2024 ADLINK Technology, Inc.
  • Page 164 Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug Page 164 Copyright © 2024 ADLINK Technology, Inc.
  • Page 165 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option (LoadImage returned error) 0xDA Boot Option is failed (StartImage returned error) 0xDB Flash update is failed 0xDC Reset protocol is not available Page 165 Copyright © 2024 ADLINK Technology, Inc.

  • Page 166: Dxe Beep Codes

    System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode. Interrupt controller is in PIC mode. Page 166 Copyright © 2024 ADLINK Technology, Inc.

  • Page 167: Oem-Reserved Checkpoint Ranges

    OEM SEC initialization after microcode loading 0x1D – 0x2A OEM pre-memory initialization codes 0x3F – 0x4E OEM PEI post memory initialization codes 0x80 – 0x8F OEM DXE initialization codes 0xC0 – 0xCF OEM BDS initialization codes Page 167 Copyright © 2024 ADLINK Technology, Inc.

  • Page 168: Software Support

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 Software Support 9.1 Windows 10 IoT Enterprise 2021 LTSC 64-bit 9.2 Ubuntu 20.04 9.3 Yocto Project* BSP tool-based embedded Linux distribution https://github.com/ADLINK/meta-adlink-x86-64bit (TBC) Page 168 Copyright © 2024 ADLINK Technology, Inc.

  • Page 169: Mechanical

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 10. Mechanical All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. Dimensions: mm Figure 5 – Module mechanical dimensions Page 169 Copyright © 2024 ADLINK Technology, Inc.

  • Page 170: Thermal

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 11. Thermal 11.1 Thermal Solutions 11.1.1 Heatspreader: HTS Dimensions: mm Figure 6 – Heatspreader: HTS Page 170 Copyright © 2024 ADLINK Technology, Inc.

  • Page 171: Heatsink: Ths-Bl

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 11.1.2 Heatsink: THS-BL Dimensions: mm Figure 7 – Heatsink: THS-BL Page 171 Copyright © 2024 ADLINK Technology, Inc.

  • Page 172: Heatsink With Fan: Thsf-Bl-S

    COM-HPC-cRLS User’s Guide PICMG COM-HPC R1.1 11.1.3 Heatsink with Fan: THSF-BL-S Dimensions: mm Figure 8 – Heatsink with Fan: THSF-BL-S Page 172 Copyright © 2024 ADLINK Technology, Inc.

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