Mode Setting - Renesas RZ/V2N Hardware Manual

RZ/V2N Evaluation Board Kit (Secure type)
2.2

Mode Setting

The table below lists the settings of the DIP switch (DSW1 on the RZ/V2N Evaluation Board) and its functions.
Table 2.2-1 DSW1 Connection Destinations and Functions
Switch No. RZ/V2N Pin
1 BOOTSELCPU
2 BOOTPLLCA_1
3 BOOTPLLCA_0
4 MD_BOOT1
5 MD_BOOT0
6 MD_CLKS
7 MD_BOOT3
8 MD_BOOT4
The table below lists the settings of the DIP switch (DSW2 on the RZ/V2N Evaluation Board) and its functions.
Table 2.2-2 DSW2 Functions
Switch No. Signal Name
1 Audio_CLKB_OE
2 Audio_CLKB
3 Audio_CLKC_OE
4 Audio_CLKC
5 NEN_VPROG
6 —
The table below lists the settings of the DIP switch (JSW1 on the RZ/V2N Evaluation Board) and its functions.
Table 2.2-3 JSW1 Functions
Switch Function
1-2 MIPI CSI-2 camera interface voltage: 1.8 V
2-3 MIPI CSI-2 camera interface voltage: 3.3 V (default)
Note: Set this switch according to the interface voltage of the camera module to be connected.
R12UZ0157EJ0110 Rev.1.10
Feb 28, 2025
Function
Select the cold boot CPU
OFF: CM33, ON: CA55 (default)
Input the CA55 frequency at the CA55 cold boot
BOOTPLLCA[1:0] = [OFF:OFF]: 1.6 GHz
= [OFF:ON]:
= [ON:OFF]:
= [ON:ON]:
Input the boot mode select signal
MD_BOOT[1:0] = [OFF:OFF]: xSPI
= [OFF:ON]:
= [ON:OFF]:
= [ON:ON]:
OFF: SSCG ON (default), ON: SSCG OFF
OFF: Normal mode (default), ON: Debug mode
Fixed to OFF
Function
OFF: Disables Audio_CLKB output of 5L35023B (default)
ON: Enables Audio_CLKB output of 5L35023B
OFF: Audio_CLKB is not supplied (default)
ON: Audio_CLKB is supplied with CLK
OFF: Disables Audio_CLKC output of 5L35023B (default)
ON: Enables Audio_CLKC output of 5L35023B
OFF: Audio_CLKC is not supplied (default)
ON: Audio_CLKC is supplied with CLK
OFF: Fixed to OFF
ON: Setting ON is prohibited
—
1.7 GHz (default)
1.1 GHz
1.5 GHz
SCIF
SD (default)
eMMC
2. Operating Procedure
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