Table 22. Ripple And Noise; Table 23. Output Voltage Timing - Intel SC5650BCDP Technical Product Specification

Power Sub-System
+3.3V
50mVp-p
3.1.5.13 Timing Requirements
The timing requirements for power supply operation are as follows. The output voltages must
rise from 10% to within regulation limits (T
allowed to rise from 1.0 to 25ms. The +3.3V, +5V and +12V output voltages start to rise at
approximately the same time. All outputs must rise monotonically. The 5V output needs to be
greater than the +3.3V output during any point of the voltage rise. The +5V output must never
be greater than the +3.3V output by more than 2.25V. Each output voltage reaches regulation
within 50ms (T ) of each other during turn on of the power supply. Each output voltage falls
vout_on
out of regulation within 400msec (T
shows the timing requirements for the power supply being turned on and off via the AC input,
with PSON held low and the PSON signal, with the AC input applied.
Item
T Output voltage rise time from each main output.
vout_rise
T All main outputs must be within regulation of each
vout_on
other within this time.
T All main outputs must leave regulation within this
vout_off
time.
* The 5VSB output voltage rise time shall be from 1.0 ms to 25 ms
24

Table 22. Ripple and Noise

+5V +12V(1,2,3,4)
50mVp-p 120mVp-p
) within 5 to 70ms, except for 5VSB which is
vout_rise
) of each other during turn off. The following table
vout_off

Table 23. Output Voltage Timing

Description
Intel order number: E80367-002
®
Intel Server System SC5650BCDP TPS
-12V +5VSB
120mVp-p 50mVp-p
Minimum Maximum
5.0* 70*
50
400
Units
msec
msec
msec
Revision 1.5