Icom IC-751A Service Manual page 30

CUSTOM IC PIN CONNECTION CPU MEMORY MAP
1 64
ADORESS BUS 15 PENS LY VCC | +5V 0000 CPU INTERNAL ROM
——_—— 0 ouT PE 14 |—___»—14 8bit x 4096W
3 62 OFFF
7 — OB7 PE 13 }——» 13
6 —+»——de6 PE 12 | 12 7 FFF | REMOTE CONTROL
5 97085 PEt po "
4 —+»——] pe4 PE 10 -—___»~10 BFFO
DATA BUS 7 8
3 97 [ 085 rEg, 9 1
2 —+=—__|0B2 PEST ——_»- 8 2
1 55/081 PE 7 |» 7 | ADDRESS 3
0 —+»—_) 080
PEG» 6 BUS
4 | Input
REMOTE SRO. rsa INT 2 PE 5 |-—» 5 5 | Matrix
MAIN DIAL a INT 1 PE 4 | —__w»— 4 6
(vss) eZ] INTO PE 3 [—» 3 7
(4+5V) —»———_| WAIT PE2—__» 2 8
16
0
BFF9
M1 PE1 | —§_» 1
16 |. 49
WRITE STROBE —«-—— | WR PEO Le 0 /
READ STROBE 7a RD
PB7 rr
QF FD |
Display Data Out(« PD549c x2}
PC7 PB 6 | —_»-28M MUTE
19 46 8 BFF | BPF(High)
201 °C& PEST A | BPF(Mid.)
VFOB +>—TrT PC 5 PB4 lags B | BPF{(Low}
22 PC4 PBS laa RIT LED(XRO) C | MODE(High)
MEMORY READ ————— PC 3 PB 2 |» CONT(PLL RESET) D | MODE(Low)
DIAL UP/DOWN acralicks Path FUNC LED E PALL
REMOTE DAV ————-|
PC 1
PB o L—____
BFFF | MS.PS
PERIPHERAL RESET P08 PAT oma
a7] Sek PAS
31 PAS CFFE | PLL Data Qut(M54929 x 2)
28 37
35182 PA 4 F800
SYSTEM RESET —s—| RESET PAS EXTERNAL RAM
"30 35 Abit x1024W( ue PD444C)
| ea Xe PA 2 }-——___ FBFF
CLOCK 31 34
(4MHz) ! —e_4x1
PAI
FFB8O
GND
82) vss pao
CPU INTERNAL RAM
~~ Cc 8bit x 128W
FREE
Fig. 13 Fig. 14
1 L/S 40
+5V —m—_J vec SCK |}—~—CLOCK
2 39 | MIC UP/DOWN INPUT
RIT/ATX | DB1 —— RUD SUD -}-——«#—UP/DOWN
DATA OUTPUT 3 38
| ope 7 ROK we | MULTIPLIER SELECT
MAIN DIAL INTA cK M2 (MAIN DIAL INPUT)
5 36
DATA OUTPUT | poo ub $1
6 | 35 MAIN DIAL SENSOR INPUT
WRITE STROBE —»—— WR s2te we
7 i 34
READ STROBE —»—— RD s3/ +
8 33 | RIT/ATX SENSOR INPUT
0 —m-—1 DA a
9 32
1 —»—) DB TS [ATS (AUTO TS)
10 1
2 —»—- 0c yo
"1 30
ADDRESS BUS 3 ob v4
INPUT 7 lo.
12 —w—1CA Y¥2 E>
13 28
13° —»—1 cB ¥3 b>
14 a7
14 —»—1 cc ¥4 MATRIX
18 26
PLL-CFFE —— X 4 YS Y DATA OUTPUT
PERIPHERAL | 16 25
ADDRESS | BPF ETC -BFXX —~-—-— X 3 ¥6 -——»—
OUTPU | 17 24
DISPLAY-9FFD —— X1 Y7 p>
18 23
CLOCK —~— CLK 2 ¥ 8 -—»—
19 22
CLK 1 Yo bo»
20 a4
GNO —«—| GND TC |} ATS THRESHOLD SET
Fig. 15
4—13