Icom IC-751A Service Manual page 28

(b) VCO
The performance of the VCO is very important for PLL
operation. A high carrier-to-noise (C/N) ratio and a stable
oscillator output is obtained in the IC-751A by using four
separate VCOs, each of which is assigned a quarter of the
necessary bandwidth. Dividing the VCOs reduces the
burden of one VCO which would otherwise provide
frequency changes over the entire bandwidth.
Power supply to the VCOs is doubly regulated as with the
reference frequency oscillator. Furthermore, coreless coils
are used for the oscillation coils in order to obtain ahigh Qas
well as immunity from external induction.
The location of grounding points on the printed circuit
board, allocation of components, and utilization of a solid
shielding case additionally give the transceiver a high C/N
ratio.
(c) LOOP SYSTEM
The output of the VCO is separated into two parts after
passing through buffer amplifier Q22.
One part is amplified by Q23, and is output to the RF UNIT as
a ist LO output after impedance matching by Q25. The
output level is about OdBm/50Q.
IN-LOOP LOCAL OSCILLATOR BLOCK DIAGRAM
The other part is fed back to the PLL loop through buffer
amplifier Q26. A common base amplifier circuit with a high
isolation performance is used for the buffer amplifier in order
to prevent spurious components from leaking into the 1st LO
output. Spurious components arise from various frequency
components in the PLL loop. The VCO signal is then mixed
with the in-loop LO (FLo) by IC3 and mixed down. Output
from the mixer passes through a bandpass filter with a
bandwidth of 35~75MHz, eliminating spurious components.
The output is then amplified by cascade amplifiers Q16 and
Q17, and is input to [C2 to form the PLL. D10 and D11 help
limit excessive input voltages to IC2.
(d) IN-LOOP LOCAL OSCILLATOR CIRCUIT
The in-loop local oscillator controls the main loop in 10Hz
steps by heterodyning the VCO signal.
Output frequency from the sub-loop is too low to use
(230.00~239.99kHz) so the output is mixed with the
reference frequency oscillator output via IC4 and converted
to an appropriate frequency through heterodyning.
Heterodyned output passes through monolithic filter FI1
where spurious components are removed. The output is
then amplified by Q15 and fed to IC3.
1C4 Fit Q15
SUB
L.P.F MIXER
B.P.F
AMP FLO ics
LOOP 7 7
REF. OSC
Q10
Fig. 11
(e) LOOP FILTER AND MUTE CIRCUITS
The loop filter of the main loop uses an active filter
composed of Q6 and Q7. The loop filter and the VCO are
important for the performance of the PLL circuits, and
determines lockup time and C/N (Carrier/Noise) ratios.
Lockup time and C/N ratios conflict with each other. Thatis,
as the time constant of the loop filter increases lockup time
speed, the C/N ratio will be decreased. In order to solve this
problem a variable resistor composed of an FET is inserted
into the loop filter in the PLL circuits. Thus, if the frequency
changes, the lockup time increases speed, decreasing the
time constant of the loop filter, and making the C/N ratio
greater by setting the time constant at a higher level than for
normal operations.
The circuit changing the time constant Q5 is driven by a
mute signal. If the mute signal is generated by the main loop
or the sub loop, or if the frequency is changed to more than a
certain level at one time, the circuit starts operating.
Mute signals output from IC1 in the main loop or 1201 in the
sub loop are processed by Q8 and Q9. They are given
appropriate voltages and a time constant, and are fed to Q5,
Q13, and Q24. Q13 and Q24 switch the bases of the tran-
sistors of the output amplifier for 1st LO and 2nd LO output.
This switching operation allows the transceiver to transmit
or receive on desired frequencies, and completes lockup
time operations more quickly.
4-4-3 SUB-LOOP
This loop forms a locked loop using a divider to provide
in-loop LO for the main loop.
The reference frequency is 5kHz and the VCO can be locked
within the frequency range of 115.00~119.995MHz. The
output signal of the 4.995MHz bandwidth with a 5kHz
resolution is divided in a 1/500 ratio by 1C204 and 1C203,
providing output ranging from 230.00 to 239.99kHz (i.e.,
9.99kHz bandwidth) in 10Hz steps. This output is fed to the
main loop.
VCO output is input to 1C202 as weil as to 1C204 and passes
through a loop filter composed of IC201 to control the VCO
and form a PLL circuit. A pulse swallow counter composed
of the combination of 1C201 and IC202, as in the main loop,
is used in this loop. Therefore the frequency can be changed
by changing the dividing ratio. A 10.24MHz reference
frequency is divided by 2 in 1C203 and then is divided by the
built-in divider of 1C201 at 5kHz.
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