All the signals generated in the PLL UNIT are produced from
a single oscillator output. Therefore, the frequencies of all
signals generated in the PLL UNIT can be calibrated simply
by adjusting the reference frequency oscillator.
REFERENCz FREQUENCY OSCILLATOR
AND MARKER CIRCUITS
The frequency of reference frequency oscillator Q10 is the
base of all the frequencies of the signals in the PLL UNIT so it
requires sufficient stability. Therefore, C3, C6, and C8 are
provided
for temperature
compensation,
and a regulator
4-4-1
PLL SUB-LOOP BLOCK DIAGRAM
output voltage of 8V is further obtained from D20, a5V zener
diode.
The
frequency
of the
reference
frequency
oscillator
is
30.72MHz. This frequency is used for the 2nd LO circuit and
for reference frequency signals for the main and sub loops,
and in-loop LO oscillator.
In
order
to
supply
the
2nd
LO
output,
the
reference
frequency oscillator output is doubled and amplified by Q14.
Spurious components are sufficiently reduced by L3, L4 and
ist bo
from LOGIC UNIT
Vv
OUT
OV1(0~8MHz)
70.55~78.45MHz
VCO SW DATA
vco SW
5V2(B~15MHz)
78.45~85.45MHz
OV3(15~22MHz) 85.45~92.45MHz
6 V4(22~30MHz) 92.45 ~100.45MHz
I
a
|
Q6, Q7
\
PHASE
|
LOOP
vcox4
|70.55~100.45MHz
p > }
1/1024
DETECTOR |
; > |
FILTER
vi~va
0 1st LO
OMAIN LOOP
|
DATA
|
|
Q18~Q21
N=3960~6950
qn | VOKHZ
|
oOSUB LOOP
|
PROGRAM-
|
PATA, | | |
MABE lq | aoa
—
soe~asmne
109
~ 23999
|
| | SWALLOW
B.PF
| | COUNTER
MIXER
1
DA
CONTROL
|
\C2
30.950
para
COUNTER
|
F11 | ~30.95999MHz
LOGIC]
ptt
_
UNIT
1710,1/41SW
BP.F
30.72MHz
REF
61.44MHz
CALO—>}
go
DOUBLER }—————> 2nd LO
Q10
Q14
IC5
IC4
10.24MHz
30.72MHz
1/3
MIXER
230
1C6
~239.999kHz
1OkHz Xn
1/1024
MARKER OUT
L.P.F
MAIN LOOP
SUB LOOP
Ic3
1/2
5.12MHz
———-|—~ ~~
ee
1C203
|
115~119.99MHz
(C204
|
PHASE
LOOP
|
11024
DETECTOR |_1
FILTER
vco
1/500
|
|
|
Q201
|
17N
5kHz
PROGRAM-|
|
ABLE IS
oan
|
|
SWALLOW
|
|
COUNTER
|
CONTROL | |
Ic2
|
/ |
COUNTER | |
|
|
1/10, 1/11SW
Fig. 8
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