Icom IC-751A Service Manual page 27

L5. An output signal of about 3dBm/500 is fed to the RF
UNIT from J5. A mute signal is applied to this stage when the
PLL is unlocked.
In order to obtain a reference signal of 10kHz for the main
loop, IC5 divides the reference frequency oscillator signal by
three and applies a 10.24MHz signal to 1C1. For a sub-loop
reference signal of 5kHz, 1C203 divides the output signal of
iC5 by two and applies a 5.12MHz signal to 1C201.
For the marker signal, a 10kHz signal is generated by
dividing the |C5 output signal of 10.24MHz by 1024 in IC6. Its
harmonics are fed through buffer amplifier Q12 and fed to
the RF UNIT through P1. Since the marker signal is derived
from reference frequency common to all the frequencies in
the PLL UNIT, all the frequencies are adjusted
simultaneously when the marker frequency is calibrated
with a standard frequency signal such as JJY or WWV.
4-4-2 MAINLOOP CIRCUITS
The main loop forms the PLL loop and supplies the 1st LO
output. It consists of a combination of a mixed down and
divided system.
The VCO output frequency Fv is given as:
Fv = FLo+ N X Fref
Frequency changes are made by changing the F_o and N.
The reference frequency (Fref) is 10kHz, and the VCO is
controlled in 10kHz steps by changing the dividing ratio N of
the programmable divider. A frequency between this step
(less than 10 kHz) is obtained by FLg which controls the
VCO output frequency. Note that FLq can be changed in
10Hz steps over the 9.99kHz range, and in this way the entire
30MHz range of the PLL can be varied in 10Hz steps.
MAIN LOOP
ICt Q6, Q7 Qi8~Q21 Q22 Q23, Q25
Reference PHASE
LOOP
Fv
Frequency F yer DETECTOR FILTER vcox4 BUFF LO AMP }+——O 1 st Lo
(10kHz)
Q26
BUFF
1C1, 1C2
(Pulse Swallow System) Q16, Q17 IC3
PROGRAMMABLE
DIVIDER AMP B.P.F MIXER
4p
1/N
Fv-FLO
|
N DATA FLO
(3960 ~6950)
In-loop LO
Fig. 9
MARKER GENERATOR MARKER
30.72MHz SWITCH "|
osc AMP 1/3 |10.24MHz | 1/1024 BUFF. MARKER OUT
AL ————— Se >
c Q10 Q11 ICc5 IC6 Q12 10kHzxn
@—> 2nd LO (Q14)
MAIN. SUB LOOP
Loop LO (IC4) REF.Frequency
Fig. 10
(a) PLLIC programmable divider which features a large dividing ratio
IC1 (M54929P) is a multi-function IC containing a phase
comparator, a programmabie divider, a reference frequency
oscillator circuit, a divider, and a swallow counter controller.
By using this IC with IC2 (M54466L, a swallow counter), it
performs pulse swallow dividing. This combination forms a
and allows operation even in a higher frequency range.
Compared to conventional ICs fewer components are
required and the combination allows the PLL to be locked in
steps as small as 10Hz.
4—10