HP Vectra Technical Reference Manual page 398

0.3 8254 Timer Controller (I/O Ports 40H
through 43H)
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The system contains an Intel Programmable Interval Timer 8254. The timer controller consists of
three separate timer channels; timer channels 0, 1 and 2. Channel 0 provides the BIOS with a
programmable time interval. Channel 1 provides the memory refresh signal of the dynamic RAMs
in the system. Channel 2 generates a fixed frequency envelope to the sound generation circuit.
WARNING!
Timer channel 1 should not be used. Writing to this channel may cause loss of data in
system memory.
The timer chip interfaces to the 80286 via 4 I/O ports:
I/O Port
040H
041H
042H
043H
Function
Counter data for timer O.
Counter data for timer
1.
Counter data for timer 2.
The· control register for all three timers.
See Intel's 8086 Family User's Manual for more details of the 8254 timer controller.
0.4 Keyboard Data Buffer (60H)
The keyboard data buffer is read by the 80286 when the keyboard asserts the OBF interrupt. The
OBF signal is automatically cleared when the data buffer is read. See Section 5 for more
information about the keyboard data buffer.
0.5 SPU Control Port (61 H)
The SPU Control Port (61 H) is a bidirectional buffer which latches an assortment of unrelated
signals. Table 0.8 describes the bit values contained in this buffer.
I/O Port Map 389