HP Vectra Technical Reference Manual page 394

Channels S thru 7 are word-wide channels so the address lines used are A 1 thru A23.
Address line AD is always forced to zero. The address register on these channels provides
address lines A 16 thru A 1 and address lines A23 through A 17 come from bits 7 through 1
of the page register. Bit 0 of the page register is not used. Care should be taken in making
sure that the counts and addresses are in words rather than bytes.
Table D.S lists I/O ports used for writing commands to the DMA controllers.
Table D.5
Controller Command I/C) Ports
Controller
1 2
1/0 \Nrite 1/0 Read
ODOH 008H
Command Register
Status Register
OD2H 009H
Request Register illegal
OD4H OOAH
Single Mask Register illegal
OD6H OOSH
Mode Register illegal
OD8H
OOCH
Clear Byte Pointer Flag illegal
ODAH OOOH
Master Clear Command
Temporary Register
ODCH OOEH
Clear Mask Command illegal
OOEH OOFH
Multi-Mask Register illegal
0.2 8259A Interrupt Controllers
The system has three 8259A inte'rrupt controllers. They are arranged as a master interrupt
controller and two slaves that are cascaded through the master. Table D.6 shows the I/O ports
for these interrupt controllers and how they are cascaded.
I/O Port Map 385