Cypress Semiconductor NoBL CY7C1470V33 Manual

Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1470V33, CY7C1472V33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V33
available in lead-free and non-lead-free 209 ball FBGA
package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• "ZZ" Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1470V33 (2M x 36)
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation
Document #: 38-05289 Rev. *I
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equiv-
alent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
and BW
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
ADDRESS
REGISTER 0
A1 A1'
D1 Q1
A0 BURST A0'
D0 Q0
LOGIC
ADV/LD
C
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
• 198 Champion Court
operations with
–BW for CY7C1474V33, BW
a h
–BW for CY7C1472V33) and a Write Enable (WE)
a b
S
D
E
A
N
T
S
A
E
MEMORY S
WRITE
ARRAY
A T
DRIVERS
E
M
E
P
R
S
I
N
E
G
INPUT INPUT
E E
REGISTER 1 REGISTER 0
,
• San Jose CA 95134-1709
CY7C1470V33
CY7C1472V33
CY7C1474V33
no wait states. The
–BW for CY7C1470V33
a d
, CE , CE ) and an
1 2 3
O
U
T
P
U
T
B
DQs
U
DQP
a
F
DQP
b
F
DQP
E
c
R DQP
d
S
E
• 408-943-2600
Revised June 20, 2006
[+] Feedback