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Cypress Semiconductor NoBL CY7C1460AV25 Manual

36-mbit (1m x 36/2m x 18/512k x 72) pipelined sram with nobl architecture
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Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 2.5V core power supply
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25, CY7C1462AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1464AV25 available in lead-free and non-lead-free
209-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• "ZZ" Sleep Mode option and Stop Clock option
Logic Block Diagram–CY7C1460AV25 (1M x 36)
A0, A1, A
MODE
CLK
C
CEN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation
Document #: 38-05354 Rev. *D
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
BURST
A0'
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
WRITE ADDRESS
REGISTER 1
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
•
198 Champion Court
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write
operations
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte
Write
Selects
(BW
BW
–BW
for
CY7C1460AV25
a
d
CY7C1462AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
S
D
E
A
N
T
S
A
E
MEMORY
S
WRITE
ARRAY
A
T
DRIVERS
E
M
E
P
R
S
I
N
E
G
INPUT
INPUT
E
REGISTER 1
REGISTER 0
,
•
San Jose
CA 95134-1709
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
with
no
wait
states.
transitions.
–BW
for
CY7C1464AV25,
a
h
and
BW
–BW
a
b
, CE
, CE
) and an
1
2
3
O
U
T
P
U
T
B
DQs
U
DQP
a
F
DQP
b
F
DQP
E
c
R
DQP
d
S
E
E
•
408-943-2600
Revised June 22, 2006
The
are
The
are
for
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Summary of Contents for Cypress Semiconductor NoBL CY7C1460AV25

  • Page 1 Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE •...

  • Page 2: Selection Guide

    Logic Block Diagram–CY7C1462AV25 (2M x 18) A0, A1, A MODE WRITE ADDRESS REGISTER 1 ADV/LD Logic Block Diagram–CY7C1464AV25 (512K x 72) A0, A1, A MODE WRITE ADDRESS REGISTER 1 ADV/LD Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Document #: 38-05354 Rev.

  • Page 3: Pin Configurations

    Pin Configurations DQPc CY7C1460AV25 (1M × 36) DQPd Document #: 38-05354 Rev. *D 100-pin TQFP Pinout DQPb CY7C1462AV25 (2M × 18) DQPb DQPa CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Page 3 of 27 [+] Feedback...
  • Page 4 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout NC/576M NC/1G NC/144M NC/72M MODE NC/576M NC/1G NC/144M NC/72M MODE Document #: 38-05354 Rev. *D CY7C1460AV25 (1M × 36) CY7C1462AV25 (2M × 18) CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 ADV/LD NC/288M ADV/LD NC/288M Page 4 of 27...
  • Page 5 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout DQPg DQPc DQPd DQPh NC/144M Pin Definitions Pin Name I/O Type Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of Synchronous the CLK.
  • Page 6 Pin Definitions (continued) Pin Name I/O Type Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous and CE Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous and CE Input-...
  • Page 7 Functional Overview The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are synchronous-pipelined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN).

  • Page 8: Truth Table

    CY7C1460AV25, BW for CY7C1460AV25 and BW a,b,c,d CY7C1462AV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep”...
  • Page 9 Partial Write Cycle Description Function (CY7C1460AV25) Read Write – No bytes written Write Byte a – (DQ and DQP Write Byte b – (DQ and DQP Write Bytes b, a Write Byte c – (DQ and DQP Write Bytes c, a Write Bytes c, b Write Bytes c, b, a Write Byte d –...

  • Page 10: Tap Controller State Diagram

    IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor- porates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 2.5V/1.8V I/O logic level. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
  • Page 11 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips.
  • Page 12 When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction.
  • Page 13 2.5V TAP AC Test Conditions Input pulse levels ... V Input rise and fall time ... 1 ns Input timing reference levels ...1.25V Output reference levels...1.25V Test load termination supply voltage...1.25V 2.5V TAP AC Output Load Equivalent 1.25V Z = 50Ω TAP DC Electrical Characteristics And Operating Conditions (0°C <...

  • Page 14: Identification Codes

    Scan Register Sizes Register Name Instruction Bypass Boundary Scan Order (165-ball FBGA package) Boundary Scan Order (209-ball FBGA package) Identification Codes Instruction Code EXTEST Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO.
  • Page 15 165-ball FBGA Boundary Scan Order CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18) Bit# Ball ID Bit# Note: 12. Bit# 89 is preset HIGH. Document #: 38-05354 Rev. *D [12] Ball ID Bit# Ball ID CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit# Ball ID Internal Page 15 of 27 [+] Feedback...
  • Page 16 209-ball FBGA Boundary Scan Order CY7C1464AV25 (512K x 72) Bit# Ball ID Bit# Note: 13. Bit# 138 is preset HIGH. Document #: 38-05354 Rev. *D [12, 13] Ball ID Bit# Ball ID CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit# Ball ID Internal Page 16 of 27 [+] Feedback...

  • Page 17: Maximum Ratings

    Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ... –65°C to +150°C Ambient Temperature with Power Applied... –55°C to +125°C Supply Voltage on V Relative to GND... –0.5V to +3.6V Supply Voltage on V Relative to GND ...
  • Page 18 [16] Capacitance Parameter Description Input Capacitance Clock Input Capacitance Input/Output Capacitance [16] Thermal Resistance Parameters Description Θ Thermal Resistance (Junction to Ambient) Θ Thermal Resistance (Junction to Case) AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT = 50Ω = 50Ω...

  • Page 19: Switching Characteristics

    Switching Characteristics Over the Operating Range Parameter Description [17] (typical) to the first access read or write Power Clock Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW Output Times Data Output Valid After CLK Rise OE LOW to Output Valid Data Output Hold After CLK Rise [18, 19, 20] Clock to High-Z...

  • Page 20: Switching Waveforms

    Switching Waveforms [23, 24, 25] Read/Write/Timing t CYC CENS CENH ADV/LD ADDRESS Data In-Out (DQ) WRITE WRITE D(A1) D(A2) [23, 24, 26] NOP, STALL and DESELECT Cycles ADV/LD ADDRESS Data In-Out (DQ) WRITE READ STALL D(A1) Q(A2) Notes: 23. For this waveform ZZ is tied low. 24.
  • Page 21 Switching Waveforms (continued) [27, 28] ZZ Mode Timing SUPPLY DDZZ ALL INPUTS (except ZZ) Outputs (Q) Notes: 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05354 Rev.

  • Page 22: Ordering Information

    Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit Speed Package (MHz) Ordering Code Diagram CY7C1460AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1462AV25-167AXC CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
  • Page 23 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit Speed Package (MHz) Ordering Code Diagram CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free CY7C1462AV25-250AXC CY7C1460AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

  • Page 24: Package Diagrams

    Package Diagrams R 0.08 MIN. 0° MIN. 0.20 MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05354 Rev. *D 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 14.00±0.10 0.30±0.08 0.65 TYP.
  • Page 25 Package Diagrams (continued) TOP VIEW PIN 1 CORNER SEATING PLANE Document #: 38-05354 Rev. *D 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) 0.15(4X) CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PIN 1 CORNER BOTTOM VIEW Ø0.05 M C Ø0.25 M C A B Ø0.45±0.05(165X) 1.00 5.00...
  • Page 26 Package Diagrams (continued) ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05354 Rev. *D ©...
  • Page 27 Document History Page Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05354 REV. ECN No. Issue Date 254911 See ECN 303533 See ECN 331778 See ECN 417547 See ECN 473650 See ECN Document #: 38-05354 Rev.

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