Structure; Single Chip Mode; Figure 2.5 Single Chip Mode - Toshiba TXZ+ TMPM4KLFYAUG Reference Manual

2.2.1. Structure

2.2.1.1. Single Chip Mode

RAMP(ch0)
CRC
CG
IB(INTIF)
IMN(INTIF)
IA(INTIF)
RLM
LVD
ADC
OPAMP
T32A
UART
PORT
TRM
OFD
A-PMD
A-ENC32
A-VE+
Flash(SFR)
Cortex-M4(with FPU)
S-Bus
S0 S1
M0
M1
M2
M3
(Note)
M4
M5
M6
M7
M8
M9
S0 S1
Clock
Synchronous
circut
DMAC NBDIF
SS0 SS1
SM0
SM1
SM2
SM3
SM4
SM5
SM6
SM7
SM8
SS0 SS1
Note: Access to Data Flash is only for DMAC

Figure 2.5 Single Chip Mode

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Clock Control and Operation Mode
D-Bus I-Bus
S2 S3
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
S2 S3
Clock
Synchronous
circut
SS2
SM0
SM1
SM2
SM3
SM4
SM5
SM6
SM7
SM8
SS2
TXZ+ Family
TMPM4K Group(2)
Code Flash
Data Flash
Boot ROM
RAM0
RAM1
RAM2
TSPI
I2C
EI2C
DNF
TRGSEL
SIWDT
NBDIF
RAMP (ch1)
DMAC(SFR)
2023-12-25
Rev. 3.0