Table of Contents
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1.4.2. Detail of Register ........................................................................................................................................................ 31
1.4.2.1. [CGPROTECT] (CG write protection register) ............................................................................................................... 31
1.4.2.2. [CGOSCCR] (Oscillation control register) ...................................................................................................................... 31
1.4.2.3. [CGSYSCR] (System clock control register) .................................................................................................................. 32
1.4.2.4. [CGSTBYCR] (Standby control register) ....................................................................................................................... 33
1.4.2.5. [CGPLL0SEL] (PLL selection register for fsys) .............................................................................................................. 33
1.4.2.6. [CGWUPHCR] (High speed oscillation warming-up register)......................................................................................... 34
1.4.2.7. [CGFSYSMENA] (Supply and stop register A for fsysm) ............................................................................................... 34
1.4.2.8. [CGFSYSMENB] (Supply and stop register B for fsysm) ............................................................................................... 37
1.4.2.9. [CGFSYSENA] (Supply and stop register A for fsysh) ................................................................................................... 38
1.4.2.10. [CGFCEN] (Clock supply and stop register for fc) ....................................................................................................... 39
1.4.2.11. [CGSPCLKEN] (Clock supply and stop register for ADC and Debug circuit) ............................................................... 39
1.5. Information according to product ..................................................................................................................... 40
1.5.1. [CGFSYSMENA] ........................................................................................................................................................ 40
1.5.2. [CGFSYSMENB] ........................................................................................................................................................ 41
1.5.3. [CGFSYSENA] ........................................................................................................................................................... 42
1.5.4. [CGFCEN] .................................................................................................................................................................. 42
2.
Memory map ............................................................................................................................................... 43
2.1. Outlines ............................................................................................................................................................ 43
2.1.1. TMPM4KxF10A .......................................................................................................................................................... 44
2.1.2. TMPM4KxFDA............................................................................................................................................................ 45
2.1.3. TMPM4KxFYA ............................................................................................................................................................ 46
2.1.4. TMPM4KxFWA ........................................................................................................................................................... 47
2.2. Bus Matrix ........................................................................................................................................................ 48
2.2.1. Structure ..................................................................................................................................................................... 49
2.2.1.1. Single Chip Mode .......................................................................................................................................................... 49
2.2.1.2. Single Boot Mode .......................................................................................................................................................... 50
2.2.2. Connection table ......................................................................................................................................................... 51
2.2.2.1. Connection of Memory related ...................................................................................................................................... 51
2.2.2.2. Connection of peripheral function .................................................................................................................................. 55
3.
Reset and power supply control ................................................................................................................. 56
3.1. Outlines ............................................................................................................................................................ 56
3.2. Description of function and operation .............................................................................................................. 56
3.2.1. Cold reset ................................................................................................................................................................... 56
3.2.1.1. Reset by a Power On Reset Circuit (without using a RESET_N pin) ............................................................................. 57
3.2.1.2. Reset by a RESET_N pin .............................................................................................................................................. 58
3.2.1.3. Continuation of reset by LVD ......................................................................................................................................... 60
3.2.2. Warm reset ................................................................................................................................................................. 61
3.2.2.1. Warm reset by RESET_N pin ........................................................................................................................................ 61
3.2.2.2. Warm reset by LVD ....................................................................................................................................................... 61
3.2.2.3. Warm reset by other internal reset ................................................................................................................................ 61
3.2.3. Starting in Single Boot Mode ...................................................................................................................................... 62
3.2.3.1. Starting by the RESET_N pin ........................................................................................................................................ 62
3.2.3.2. Starting in Single Boot Mode when power supply is stable ............................................................................................ 63
3.2.4. Power On Reset Circuit .............................................................................................................................................. 64
Clock Control and Operation Mode
3 / 68
TXZ+ Family
TMPM4K Group(2)
2023-12-25
Rev. 3.0
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