Warm Reset; Warm Reset By Reset_N Pin; Warm Reset By Lvd; Warm Reset By Other Internal Reset - Toshiba TXZ+ TMPM4KLFYAUG Reference Manual

32-bit risc microcontroller
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3.2.2. Warm reset

3.2.2.1. Warm reset by RESET_N pin

When resetting with the RESET_N pin, set the RESET_N pin to "Low" for 17.2 µs or more while the power
supply voltage is within the operating range.
When the "Low" period of a RESET_N pin is longer than "Internal processing time", after a RESET_N pin
changes to "High", Internal reset is released after "CPU operation wait time" elapsed.
When the "Low" period of a RESET_N pin is shorter than "Internal processing time", after internal reset is
extended and from a RESET_N pin changes to "Low", Internal reset is released after "Internal processing time" +
"CPU operation wait time" has elapsed.
DVDD5
When RESET_N pin reset time is longer than internal processing time(t
RESET_N pin
Internal reset
When RESET_N pin reset time is less than internal processing time(t
RESET_N pin
Internal reset

3.2.2.2. Warm reset by LVD

LVD reset is performed correctly when the LVD reset voltage or less and the power supply voltage is within the
operating voltage range. When the power supply voltage drop period is longer than the "internal processing time",
internal reset is released after "internal processing time" has elapsed, LVD release voltage has been exceeded, and
"LVD detection release time" + "CPU operation wait time" has elapsed. When the power supply voltage drop
period is shorter than the "internal processing time", internal reset is released after "internal processing time" +
"CPU operation wait time" has elapsed from LVD reset is detected.

3.2.2.3. Warm reset by other internal reset

In case of reset asserted by internal factors, such as SIWDT, OFD, LOCKUP, and <SYSRESETREQ>, Internal
reset is released after "Internal processing time" + "CPU operation wait time" elapsed.
Operating voltage range
Internal processing time(
Internal processing time(

Figure 3.5 Warm reset operation

Clock Control and Operation Mode
)
IRST
t
)
IRST
)
IRST
CPU Operation
start
t
t
)
CPU operation wait time (
IRST
61 / 68
TXZ+ Family
TMPM4K Group(2)
DVDD5=DVDD5A=DVDD5B=AVDD5
CPU Operation
start
t
CPU operation wait time (
)
CPUWT
)
CPUWT
2023-12-25
Rev. 3.0

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