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4.
LINKING TO THE AnACPU (WITH DEDICATED INSTRUCTIONS)
AND THE AJ71 PT32-S3
MELSEC-A
When data is written
to two
or more addresses in the buffer of an
A64RDC, a single TO instruction can execute data write if the addresses
are sequential. If the addresses are not continuous,
it is necessary to
execute the TO instruction at two or more points as shown below. In this
case, two or more TO instructions are stored in the request-to-communi-
cate registration areas.
TOP
K1
K1
H501
K1
' 1 "
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I
1
LEDR
If an attempt is made to store TO instruction information which is larger
than the number of vacant areas in request-to-communicate registration
areas, an error occurs and
the CPU stops operating. To prevent this,
confirmation that the vacancy in the request-to-communicate registra-
tion areas is larger than theTO instruction information must be provided.
The programming example below shows what happens when the
TO
instruction is executed after a vacancy in the request-to-communicate
registration areas is confirmed.
r-------.....---
' - - - - - - - - - ' - - - - " " - - - - -
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Example:
:
Initial setting program for an A64RDC
'
Channel designation
(buffer address
0)
Channels 1 and
3 '
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Averaging designation (buffer address
1)
Channel
1
averaging time (buffer address 2)
1000
[msec]
,
Channel
3
averaging count (buffer address 4)
10
[times]
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I
, - - - - - - - - - - - - - . - - - - - - - . - - - - - . - - - - - -
Initial setting Conversion
Confirmation of a vacancy in the request-
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t
[
PRC
1
M i
1
YO
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LEDR
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-
1
4-
29
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