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5. LINKING
TO
AN ACPU AND AN AJ71 PT3243
MELSEC-A
(4)
If a communications-completed response signal to the send executed to
the A64RDC is not transmitted back, the
CPU goes into infinite-wait
status unless
the CPU module is reset. To prevent this, provide a
monitoring timer to allow retransmission
of the same data at preset
intervals.
pH'
I
TO
Y(n+O)
- 1
RST
Request-to-send signal is reset.
TOP
I
( n l )
I
K858
I
(n2)
I
K1
1
TOP
( n l )
K859
(n3)
Received-data
request-totlear signal
Data stored in the remote
,terminal receive area of the
master module is cleared.
-
The communications-enabled
X(n+23), Y(n+O) and Y(n+23) are control I/O signals for the AJ71 PT32-
S3 (see Section 5.3.2 for details).
The contents of ( n l ) , (n2), and (n3) designated by each instruction are
as described below.
( n l ) : Higher two digits
of the head 1/0 number assigned to an
AJ35PT32-S3.
Example) "12H" when assigned to X/Y120 to 13F
(n2): Receive
buffer cleared/not cleared setting for each remote
terminal number.
b 1 5
to
b O
_ .
0
0
f
t
t
I
I
For remote terminal module No. 1
For remote terminal module No. 2
For remote terminal module No. 14
0
: Not cleared
1 : Cleared
The setting contents are written to address
858
in the buffer of
the AJ71 PT32-S3.
5 - 2 7
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