Advertisement
5.
LINKING TO AN ACPU AND AN AJ71 PT3243
MELSEC-A
5.3
1 / 0 Signals Handled with the PC
CPU
5.3.1
I/O signals of an A64RDC
This section describes the functions
of the control I/O signals transmitted
between the A64RDC and an AnACPU. Devices X refer to the input signals
from the A64RDC to the AnACPU. Devices Y refer to the output signals from
the AnACPU to the A64RDC.
Table 5.1 List of A64RD3C I/O Signals
I
Signal Direction
: A64RD3C
-
ACPU
I
Signal Direction
: ACPU
- .
A64RD3C
I
Device No.
I
Description
Description
I
?
I
Unusable
I
x 4
Y4
I
X5
I
Reset
switch
ON-detected flag
I
y5
I
Reset switch ON-detected flag
reset signal
X6
X1 7
to
READY flag X1
8
Unusable
x 1 9
x 1
c
CH3 : Disconnection detection flag
X1
B
CH2 : Disconnection detection flag
X1 A
CH1 : Disconnection detection flag
X1 D
CH4 : Dixonnection detection flag
to
X1 F
Unusable
y6
y1
to
Reset switch ONdetected flag
reset signal
~
~~
Table
5.2
A64RD4C I/O Signals
I
Signal Direction
: A64RD4C
- .
A2CCPU
I
Signal Direction
: A2CCPU
- .
A64RD4C
I
Device No.
I
Description
I
Device No.
I
Description
I E I
Unusable
Unusable
x 5
Reset switch ON-detected flag
Reset switch ONdetected flag
y5
reset signal
X6
to
X1 7
Unusable
X1 8
READY flag
Y6
x 1
9
to
1
Disconnection detection flag
Y1F
Unusable
X1 D
X1 F
to
Unusable
IMPORTANT
I
If any unusable I/O signals are utilized
in the sequence program, the
functions of the A64RDC cannot be guaranteed.
5 - 9
Advertisement
