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5 .
LINKING TO AN ACPU AND AN AJ71 PT32-S3
MELSEC-A
MELSECNET/MINI-S3 link communications start
2
Data register zero clear
M9038
+I
Zero
clear
data
registers
DO to D l 3
Control I/O signal batch refresh (read)
13
v'
_______I
FROM
I
1
K,
,o
I
K4X1
OO
I
e
The contents
of the batch refresh
received-data area of the master
23
34
37
39
Error code
Y ;
, 7
T l
The FROM/TO instruction error
detection (X24) is turned ON, and the
error code is stored in register
DO.
X030
X024
+ H
YMD
Error
reset
Disconnection detection
x 1 19
+ I
CH1
disconnection
detection
X1 1A
+ I
CH2
disconnection
detection
W
Initial setting write command
SET
I
M l
t
RST
I
M1
PLS
M2
45 k ; 3 8
5 - 31
The A64RD3C hardware is reset,
, and the initial setting write command
signal (M2) is turned ON when the
AnACPU is
put
into the RUN state.
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