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3 .
LINKING TO THE A2CCPU
MELSEC-A
(5)
If a communications-completed response signal to the send executed to
the A64RDC is not transmitted back, the CPU module is set in the state
waiting for the communications-completed signal infinitely unless the
CPU module is reset. To prevent this, provide a monitoring timer to allow
retransmission of the same data at preset time intervals.
M9081
TOP
I
K1
I
K O
I
W
I
K5
I
PRC
1 -
Communicationscompleted
r - - - - 7
response wait flag
'
K20
*
Communications
allowance time
Set by user
1
X (n
+
7)
L - - - - J
In the above circuit, provide one
block for each remote terminal
module.
X(n+7), Y(n+7), and Y(n+4) are control
I/O
signals
for the A64RDC (see Section 3.3).
(6)
When averaging is to be designated
for the A64RDC, the data of the
conversion-enabled/disabled designation, averaging designation,
averaging time, and averaging count can be written to the buffer without
restriction when they are written with one
TO instruction. If they are
written with several TO instructions, follow the order shown below.
Conversion-enabledldisabled designation
-
Averaging time or count
-
Averaging designation
7
Must be written last.
3-24
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