Uart - Quectel RG255C-GL Hardware Design

Module
USB_DM
USB_DP
GND
A common mode choke L1 is recommended to be added in series between the module and your MCU to
suppress EMI spurious transmission. Meanwhile, the 0 Ω resistors (R1 and R2) should be added in series
between the module and the test points to facilitate debugging, and the resistors are not mounted by
default. In order to ensure the integrity of USB data line signal, L1, R1, and R2 components must be
placed close to the module, and also these resistors should be placed close to each other. The extra
stubs of trace must be as short as possible.
To meet USB 2.0 specification, the following principles should be complied with when design the USB
interface.
⚫
Route the USB signal traces as differential pairs with ground surrounded. The impedance of USB
differential trace is 90 Ω.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. Route
the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that
layer and with ground planes above and below.
⚫
Junction capacitance of the ESD protection device might cause influences on USB data traces, so
you should pay attention to the selection of the device. Typically, the capacitance value should be
less than 2 pF.
⚫
Keep the ESD protection components as close to the USB connector as possible.

4.3. UART

RG255C-GL Mini PCIe provides one main UART that supports 115200 bps, 9600 bps, 19200 bps, 38400
bps, 57600 bps, and 230400 bps baud rates, and the default is 115200 bps. It supports RTS and CTS
hardware flow control, and can be used for AT command communication and data transmission.
The following table shows the pin definition of the interface.
RG255C-GL_Mini_PCIe_Hardware_Design
Minimize these stubs
R1
R2
L1
ESD Array Close to Module
Figure 7: Reference Circuit of USB Interface
Test Points
NM_0R
NM_0R
5G Module Series
MCU
USB_DM
USB_DP
GND
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