Configure Digital Input (Rev. 1); Configure Digital Input (Rev. 2); Configure Digital Output Channels - Ametek DN VR-608 Series User Manual

4.5.3 Configure
Digital Input
(Rev. 1)
//Configure Channel 4 to count teeth over a specific time interval.
CUeiVRChannel* vr4 = vrSession.CreateVRChannel(
//Set the zero crossing level to a positive value, e.g. 0.8 V.
vr4->SetZCMode(UeiZCModeFixed);
vr4->SetZCLevel(0.8);
//Set the APT mode to Logic
vr4->SetAPTMode(UeiAPTModeLogic);
//Store data at a rate of 10 Hz. Always set to less than input_freq/2.
vr4->SetTimedModeRate(10);
4.5.4 Configure
Digital Input
(Rev. 2)
//Configure counter-timer 6 to count teeth over a specific time interval.
CUeiVRChannel* vr6 = vrSession.CreateVRChannel(
//Set zero crossing mode to ZC_ONCHIP
vr6->SetZCMode(UeiZCModeChip);
//Route DIn0 to counter-timer module on channel 6.
vr6->SetSource(UeiVRSourceTTL0);
//Store data at a rate of 10 Hz. Always set to less than input_freq/2.
vr6->SetTimedModeRate(10);
4.6 Configure
Digital Output
Channels
© Copyright 2024
United Electronic Industries, Inc.
You can read TTL-level digital pulses through the VR front-end by configuring
the board for ADC-based zero crossing detection (i.e., either UeiZCModeFixed
or UeiZCModeLogic mode). The following example uses the Fixed zero
crossing mode to read a digital sensor wired to In4+/-.
This functionality is supported on both Rev. 1 and Rev. 2 boards, though we
recommend Rev. 2 users route digital signals directly to the counter-timer
modules as described in Section 4.5.4
On Revision 2 boards, TTL-level digital pulses on DIn can connect directly to the
counter-timer modules. When a counter-timer is used for TTL inputs, it is
disconnected from the VR input. Peak threshold settings are ignored and while
zero crossing detection is bypassed, the zero crossing mode must be set to
ZC_ONCHIP.
A TTL input can connect to multiple counter-timers if desired.
The CreateSimulatedVRChannel() method adds a digital output channel
to the session. The vr0:3 resources correspond to DOut[0:3] respectively.
Supported digital output signals are summarized in Section 2.2.5.
February 2024
DNx-VR-608 Variable Reluctance Interface
Programming with the High-level API
"pdna://192.168.100.2/Dev2/vr4",
UeiVRModeCounterTimed);
"pdna://192.168.100.2/Dev2/vr6",
UeiVRModeCounterTimed);
Chapter 4 32
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