Logic Block Diagram For A Dual Vr Ic Channel; Adaptive Peak Threshold (Apt) From The Max9926 Specification - Ametek DN VR-608 Series User Manual

2RX/1TX ARINC-429 transceiver protocol controllers (FPGA/DSP control/access Block 1) 2RX/1TX ARINC-429 transceiver protocol controllers (FPGA/DSP control/access Block 1)
2.2.2.2 Peak
Threshold
Levels
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United Electronic Industries, Inc.
threshold to determine when cout should be dropped. The peak threshold
allows the comparator to ignore zero crossings due to noise. The resulting
digital output signal is illustrated in Figure 2-2.
MAX 9926 Channel 0
In -
0
Limiter Clipper
In +
0
Circuit Circuit
Figure 2-6 Logic Block Diagram for a Dual VR IC Channel
Setting a peak threshold level introduces hysteresis to the zero crossing
detector. The DNx-VR-608 provides the following peak threshold
configurations:
• VR608_APT_ONCHIP: automatically adjusts the threshold to 1/3 of the
peak of the previous analog input cycle, using the built-in APT detector
of the Dual VR IC (see Figure 2-7). Note that if the input voltage
remains lower than the adaptive threshold for 85 ms, the threshold will
be dropped to the chip's minimum value, driving the comparator output
low; this ensures pulse recognition in the presence of an intermittent
sensor connection.
• VR608_APT_LOGIC: calculated as (max)/2^n, where n=1, 2, 3, or 4
and "max" is the moving average of previous analog input peaks (Rev. 2
only).
ADAPTIVE
THRESHOLD
SET BY V1
1
V1
3
VR V1
SIGNAL
COUT
20ms 40ms
Figure 2-7 Adaptive Peak Threshold (APT) from the MAX9926
February 2024
DNx-VR-608 Variable Reluctance Interface
-
Amplifier
+
1/3
Input Voltage
Peak Detector
ONCHIP peak
threshold
ONCHIP zero
crossing level
FIXED or LOGIC peak
threshold from DAC
ADAPTIVE
THRESHOLD
SET BY V2
V2
1/3 V2
60ms 80ms 100ms 120ms
Specification
Chapter 2
Functional Description
-
cout0
Comparator
+
MIN
THRESHOLD
85ms
140ms 160ms 180ms 200ms
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