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2.2
DNx-VR-608
Device
Architecture
DIn0 <rev. 2>
DOut0
2.2.1
Inputs
© Copyright 2024
United Electronic Industries, Inc.
A simplified block diagram of the DNx-VR-608 Variable Reluctance Interface
board is illustrated in Figure 2-5.
VR-608 Channel Pair 6/7
VR-608 Channel Pair 4/5
VR-608 Channel Pair 2/3
VR-608 Channel Pair 0/1
ADC
PGA
V
TH0
DAC
PGA
In
+
0
Clip & Comparator 0
In
-
0
MAX 9926
Dual VR IC
In
+
1
In
-
Clip & Comparator 1
1
DAC
PGA
V
TH1
ADC
PGA
Optical Isolation Boundary (Per Channel Pair)
Figure 2-5 Simplified Block Diagram of the DNx-VR-608
The front-end of the DNx-VR-608 exposes eight differential analog inputs
through the DB-37 connector. The eight channels are grouped and isolated in
pairs (0&1, 2&3, 4&5, 6&7), where each pair can accept either two individual VR
sensors or one out-of-phase dual VR sensor. Revision 2 boards also provide
four TTL-level digital inputs which route directly to the counter timer modules.
The DNx-VR-608 is designed to accept the following input signal sources:
•
AC waveform from a VR sensor - The VR sensor's signal and return
wires connect to a single channel (e.g., In
supports systems with or without a zero/index/z-tooth.
•
AC waveforms from a dual VR system - The two VR sensors are
connected to a channel pair (e.g., one sensor on In
one on In
+/- of Channel 1). The board detects rotational direction
1
("dirn") by checking for the leading channel. Revision 2 boards can also
measure the phase shift between the two channels; this feature is used
to compute torque in setups where one toothed wheel is under torque
and the other is not.
February 2024
DNx-VR-608 Variable Reluctance Interface
Boot/Store Flash
FPGA
VR-608 Logic
ch0_volts
FIR
<rev. 2>
ADC ZC Detector
cout0
Counter/
Timer 0
dirn
Counter/
cout1
Timer 1
ADC ZC Detector
ch1_volts
FIR
<rev. 2>
ttl_in
Digital Output
Selector
Ch 2/3, 4/5, 6/7 Logic
+/- of Channel 0). The board
0
Chapter 2
Functional Description
Sync 3
Sync 2
Sync 1
Sync 0
<rev. 2>
+/- of Channel 0 and
0
www.ueidaq.com
508.921.4600
12
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