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5.4.1.4
Digital Input
Configuration
(Rev. 2)
//Count teeth over a specific time interval. For higher rates (over
//10 kHz) an FIR filter can be enabled by ORing in
//DQ_VR608_FLAG_CH_FIR_ENABLE,
mode = DQ_VR608_MODE_COUNTER|DQ_VR608_MODE_TIMED;
//Store data at a rate of 10 Hz. Always set to less than input_freq/2.
//Route DIn0 to counter-timer module on channel 6.
extcfg.cfg_flags |=
DQ_VR608_CFGVLD_TMODE_RATE |
DQ_VR608_CFGVLD_TTL_CFG;
extcfg.tmode_rate = 10;
extcfg.ttl_cfg = DQ_VR608_TTL_SRC(1, 6, 0);
//Set zero crossing mode to ZC_ONCHIP
front_cfg = DQ_VR608_ZC_ONCHIP
//Program mode and tmode_rate on channel 6.
//ttl_cfg is programmed for the entire layer.
DqAdv608SetCfgExt(hd, DEVN, 6, front_cfg, mode, &extcfg);
© Copyright 2024
United Electronic Industries, Inc.
This functionality is supported on both Rev. 1 and Rev. 2 boards, though we
recommend Rev. 2 users route digital signals directly to the counter-timer
modules as described in Section 5.4.1.4.
On Revision 2 boards, TTL-level digital pulses on DIn can connect directly to the
counter-timer modules. When a counter-timer is used for TTL inputs, it is
disconnected from the VR input and ignores front_cfg settings. However,
while zero crossing detection is bypassed, zero crossing mode must be set to
ZC_ONCHIP.
February 2024
DNx-VR-608 Variable Reluctance Interface
Programming with the Low-level API
Chapter 5
48
www.ueidaq.com
508.921.4600
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