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2.2.4.1
Counter/Timer
Modes
© Copyright 2024
United Electronic Industries, Inc.
The internal structure of a Counter/Timer module is shown in Figure 2-8.
IN
from Dual VR IC,
ADC Module,
DIn <rev. 2>,
or Torque Module <rev. 2>
OUT
to DOut
Output control logic, creates output
signal based on the current mode
and value of main counter
CRH Capture Register HI
CRL Capture Register LO
STR Status
Register
Figure 2-8 DNx-VR-608 Counter/Timer Module
Results from the counting process are stored in the CRR, CR, CRH, and CRL
registers. The data stored in these registers depends on the counting mode as
described in Section 2.2.4.1.
Count register data can optionally be time stamped and copied over into the
input FIFO; this feature is useful for tracking how the data changes over time.
Either the FIFO or immediate register values may be read upon request from the
firmware. Users can configure the FIFO watermark level to control data flow
from the Cube/Rack.
The following Counter/Timer modes are per-channel configurable:
•
Timed: counts the number of pulses in a given time interval.
•
Timed Pulse Period Measurement (TPPM): counts the number of
edges detected within a default measurement window in order to
calculate RPM. Two cycles of the input waveform are needed for the
velocity calculation. The measurement window may be dynamically
increased by a configurable timeout period to accommodate slower
input frequencies so that the measurement can be completed. TPPM is
for continuous signals only, i.e., wheels with no Z-tooth (Revision 2 only)
•
Z-Pulse: counts the number of pulses and time interval between
missing or fused Z-tooth detections.
•
N-Pulse: measures the time to detect a given number of pulses.
February 2024
DNx-VR-608 Variable Reluctance Interface
Z-pulse detector
CRR count (resettable) register
CR count register
PC period count register
66MHz base clock
31-bit Timebase
TBR Register
IFIFO
Input FIFO
Chapter 2
Functional Description
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