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5.4.1.5
Alarm
Configuration
(Rev. 2)
//Set DOut0 to pulse high when input is open on Ch0 and/or Ch1.
extcfg.cfg_flags |=
DQ_VR608_CFGVLD_ALARM_SRC |
DQ_VR608_CFGVLD_D_OUT;
extcfg.alarm_src =
DQ_VR608_CFG_ALARM0_OPEN0 |
DQ_VR608_CFG_ALARM0_OPEN1;
extcfg.d_out = DQ_VR608_DBG_N(
DQ_VR608_CFG_DO_DBG_OFF,
DQ_VR608_CFG_DO_DBG_OFF,
DQ_VR608_CFG_DO_DBG_OFF,
DQ_VR608_CFG_DO_ALARM0);
5.4.1.6
Digital Output
Dividers
(Rev. 2)
//Divide by 4 on DOut3, Divide by 2 on DOut2,
//Divide by 2 and invert output on DOut1, no division on DOut0
extcfg.cfg_flags |=
DQ_VR608_CFGVLD_DO_DIV |
DQ_VR608_CFGVLD_D_OUT;
extcfg.dout_div = DQ_VR608_DOUT_DIV(
DQ_VR608_DIVSEL_4,
DQ_VR608_DIVSEL_2,
DQ_VR608_DIVSEL_2_I,
DQ_VR608_DIVSEL_1);
© Copyright 2024
United Electronic Industries, Inc.
On Revision 2 boards, you can configure digital outputs as any combination of
open circuit, stalled rotation, or overspeed alarms. An alarm can only be
assigned to DOut on the same channel block, e.g., Alarm0 to DOut0.
Use the stall_lvl member of the DQ_VR608_CFG_R2 structure to set a noise
floor for open/stalled alarms. Use ov_speed to specify RPM for overspeed
alarms.
On Revision 2 boards, dividers can be independently applied to the digital
outputs. Dividers of 2, 4, 8, or 16 are supported. The output pulse will always
have a 50% duty cycle. To set divider values, use the DQ_VR608_DOUT_DIV
macro to populate the dout_div member of the DQ_VR608_CFG_R2 structure.
The macro takes arguments for each of the digital output lines (D3...D0) in the
form of one of the DQ_VR608_DIVSEL values. The digital output signals can
also be inverted. Please refer to the "PowerDNA API Reference Manual" for a
complete list of supported divider values.
February 2024
DNx-VR-608 Variable Reluctance Interface
Programming with the Low-level API
Chapter 5
49
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