HP 8133A Service Manual page 155

The
The Output Amplifier
Bitstream Trigger Retiming
The bitstream trigger signal is also generated in this gatearray. The
memory clock (MEMCLK) signal is used for this purpose.
A PLL is usled to generate a negative delay to compensate for the long
delay throu,gh the data generator and to ensure the right timing with
respect to the multiplexer over the whole frequency range.
a digital phase and frequency sensitive ECL
The phase detector is
type with a maximum operation frequency of 80 MHz. It must have a
range of 7 octaves.
The loop filter is a symmetrical low pass filter comprising an
instrumentation amplifier and a PI (proportional integration) regulator.
Gain switching of the filter
resistors and a switchable double T attenuator.
The differential output of the Multiplexer provides the input signals
to the Output Amplifier. Voltage and current sources, some of them
programmable via the device bus interface, are used for biasing and
programming the output amplitude and high level. Two voltage
sources and two current sources are programmable to adjust the pulse
performance over frequency and temperature.
The amplifier consists of 2 identical, full-custom GaAs ICs packaged
on a
thickfilm hybrid. All voltage and current sources needed for the
amplifier are located on the PC-Board and are decoupled by capacitors
on the PC-board, in addition to printed bypass capacitors on the
hybrid.
The ferrite:; F1 -
and the optional ferrites F5 and F6 reduce
F4
HF-ringing below lOGHz, improving output performance.
The retimirig which is done for the data bits in the multiplexer is
also required for the bit 0 trigger signal, to avoid internal PLL jitter
appearing at the output.
realized by varying the gain controlling
is
Theory of Operation 7-23