HP 8133A Service Manual page 139

Device Bus Timing
DTACK Generation
and Wait State Generation
The wait state signals and the signals GATE2 and GATE3 are
generated by two D-type flip flops (U35) and the 8 bit shift register
The outputs of the shift register are also used to generate wait states
(to delay the DTACK generation by a number
OR'ed with the appropriate chip select lines). Table 3 shows the
number of wait states that can be achieved by the various signals.
address ranges. One wait cycle equals one clock period (125 ns). A
read or wri1;e cycle without any wait states takes four clock cycles
3B
-
The DTACK generation is not complex. U6A, U6B and U33B are
connected together as an AND gate with eight inputs. The chip select
signals (listed in table 1) are fed into this AND gate either directly (i.e.
zero
with wait states), or OR'ed with one of the wait state signals
(listed in taliles 3 and 1). For the MFP, the DTACK signal (U21, pin
is used instead of the chip select line.
Other address decode signals
7-2.
signal name derived from
+
LCSEPROML LCSEPROM LDS
+
LCSEPROMU LCSEPROM UDS
+
LCSRAML LCSRAM LDS
+
LCSRAMU LCSRAM
UDS
+
LDS
LUDWRITE UDS
LLDREAD (not RD/WR)+LDS
+
LUDREAD
HLDREAD
LIACK AS+ (not(FOC.FCl.Fc2))
-
3B
Signal number of wait states
not 2Q of U36 1
not QA of US 2
not QB of US 3
not QC of US
4
not QD of US
not QE of US 6
not QF of US
not
QG of U6 8
not QH of US
9
clock cycles when
of
46)
Operation 7-7
Theory of