HP 8133A Service Manual page 142

Frequency Counter
Serial I/O
Reset and Battery Backup
Operation
-
3C
The gate array FACE is used as the frequency counter. The frequency
signal from the timing board is fed directly into the FVFC pin
gate array. The reference clock is 8 MHZ.
See LAB-10.
-
3A
The reset generation and battery backup is controlled by the pP
control circuit U15. When the
low and keeps the microprocessor and the other circuits
state. The two RAM ICs and the OR-gate U7 (which drives the chip
select lines of the RAMS) are supplied from Vout (U15, Pin 2) which
in turn is supplied from the backup battery. When the supply voltage
exceeds 4.65V the BATT-ON signal (U15, Pin 5) goes low and turns
on transistor Q1 which connects the
After approximately 50 ms the RESET line goes high and releases the
microprocessor from the reset state.
+
Sheet) the RESET line (U15, Pin 15) is
+
of
the
a define
in
+