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Table 3.6.3 I/O Registers and Their Specifications (2/2)
Port
Name
Port 8
P80
P81
P82
P83
P84
P85
P86
P87
Port 9
P90
P93 to P96
P93
P94
P95
P96
Port A
PA3
PA0 to PA7
X: Don't care
Note 1: When PA1 to PA4 are used as AD converter input channels, a 3-bit field in the AD mode control
register ADMOD1<ADCH2:0> is used to select the channel.
Note 2: When PA0 is used as the
input.
Specification
Input port (without PU)
Input port (with PU)
Output port
TXD0 output
Input port/RXD0 input (without PU)
Input port/RXD0 input (with PU)
Output port
Input port/SCLK0/CTS0 input (without PU)
Input port/SCLK0/CTS0 input (with PU)
Output port
SCLK0 output
Input port (without PU)
Input port (with PU)
Output port
output
STS
0
Input port (without PU)
Input port (with PU)
Output port
TXD1 output
Input port/RXD1 input (without PU)
Input port/RXD1 input (with PU)
Output port
Input port/SCLK1/CTS1 input (without PU)
Input port/SCLK1/CTS1 input (with PU)
Output port
SCLK1 output
Input port (without PU)
Input port (with PU)
Output port
output
STS
1
Input port
Output port
INT5 input
Input port
Output port
TB0IN0 input
TB0IN1 input
TB0OUT0 output
TB0OUT1 output
Input port
input
ADTRG
Input port
AN0 to AN7
input, ADMOD1<ADTRGE> is used to enable external trigger
ADTRG
91C829-44
TMP91C829
I/O Registers
Pn
PnCR
PnFC
0
0
0
1
0
0
X
1
0
X
1
1
0
0
None
1
0
X
1
0
0
0
1
0
0
X
1
0
X
1
1
0
0
0
1
0
0
X
1
0
X
1
1
0
0
0
1
0
0
X
1
0
X
1
1
0
0
None
1
0
X
1
0
0
0
1
0
0
X
1
0
X
1
1
0
0
0
1
0
0
X
1
0
X
1
1
X
0
0
X
1
0
X
0
1
X
0
X
1
None
X
0
X
0
X
1
1
X
1
1
X
X
None
X
X
2006-03-15
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