Toshiba TLCS-900/L1 Series Manual page 155

The watchdog timer consists of a 22-stage binary counter which uses the system clock
(f ) as the input clock. The binary counter can output f
SYS
f /2 .
21
SYS
WDT counter
n
WDT interrupt
WDT clear
(Soft ware)
The runaway is detected when an overflow occurs, and the watchdog timer can reset
device. In this case, the reset time will be between 22 and 29 states (19.6 to 25.8 μs at f
= 36MHz, f
OSCH
oscillator clock (f
n
WDT counter
WDT interrupt
Internal reset
Overflow
Figure 3.12.2 Normal Mode
= 2.25 state) is f /2, where f
FPH
) by sixteen through the clock gear function.
OSCH
Overflow
22 to 29 states
(19.6 to 25.8 μs at f
OSCH
Figure 3.12.3 Reset Mode
91C829-153
/2
15
SYS
Clear write code
is generated by dividing the high-speed
FPH
= 36 MHz, f = 2.25 MHz)
FPH
TMP91C829
, f /2 , f /2 and
17 19
SYS SYS
0
FPH
2006-03-15