Toshiba TLCS-900/L1 Series Manual page 138

a. Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the
TXD0 and SCLK0 pins respectively each time the CPU writes the data to the
transmission buffer.
When all the data has been output, INTES0<ITX0C> is set to 1, causing an
INTTX0 interrupt to be generated.
Timing to write
transmission data
SCLK0 output
(<SCLKS>=0
Rising edge mode)
SCLK0 output
(<SCLKS>=1
Falling edge mode)
TXD0
ITX0C
(INTTX0
Interrupt request)
Figure 3.10.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode)
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
input becomes active after the data has been written to the transmission buffer by
the CPU.
When all the data has been output, INTES0<ITX0C> is set to 1, causing an
INTTX0 interrupt to be generated.
SCLK0input
(<SCLKS> = 0
Rising edge mode)
SCLK0 input
(<SCLKS> = 1
Falling edge mode)
TXD0
ITX0C
(INTTX0
Interrupt request)
Figure 3.10.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode)
Bit0 Bit1
(Channel 0)
Bit0 Bit1
(Channel 0)
91C829-136
Bit6
Bit5 Bit6 Bit7
TMP91C829
(Internal clock
timing)
Bit7
2006-03-15