Toshiba TLCS-900/L1 Series Manual page 22

(2) How to clear a HALT mode
The halt state can be cleared by a reset or by an interrupt request. The combination
of the value in <IFF0:2> of the interrupt mask register and the current HALT mode
determine in which ways the HALT mode may be cleared. The details associated with
each type of halt state clearance are shown in Table 3.4.3.
• Clearance by interrupt request
Whether or not the HALT mode is cleared and subsequent operation depends on
the status of the generated interrupt. If the interrupt request level set before
execution of the HALT instruction is greater than or equal to the value in the
interrupt mask register, the following sequence takes place: The HALT mode is
cleared, the interrupt is then processed, and the CPU then resumes execution
starting from the instruction following the HALT instruction. If the interrupt
request level set before execution of the HALT instruction is less than the value in
the interrupt mask register, the HALT mode is not cleared. (If a non-maskable
interrupt is generated, the HALT mode is cleared and the interrupt processed,
regardless of the value in the interrupt mask register.)
However, for INT0 to INT4 only, even if the interrupt request level set before
execution of the HALT instruction is less than the value in the interrupt mask
register, the HALT mode is cleared. In this case, the interrupt is not processed and
the CPU resumes execution starting from the instruction following the HALT
instruction. The interrupt request flag remains set to 1.
Note: Usually, interrupts can release all halts status. However, the interrupts (
INT0 to INT4) which can release the HALT mode may not be able to do so if
they are input during the period CPU is shifting to the HALT mode (for about 5
clocks of f
(In this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficulty. The priority of this interrupt is
compared with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
•
Clearance by reset
Any halt state can be cleared by a reset.
When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms)
must be allowed after the reset for the operation of the oscillator to stabilize.
When a HALT mode is cleared by resetting, the contents of the internal RAM
remain the same as they were before execution of the HALT instruction. However,
all other settings are reinitialized. (Clearance by an interrupt affects neither the
RAM contents nor any other settings – the state which existed before the HALT
instruction was executed is retained.)
) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).
FPH
91C829-20
TMP91C829
,
NMI
2006-03-15