Toshiba TLCS-900/L1 Series Manual page 108

(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the up
counter UC0 matches the value set in this timer register, the comparator match detect
signal will go active.
Setting data for both upper and lower registers is always needed. For example,
either using 2-byte data transfer instruction or using 1 byte date transfer instruction
twice for lower 8 bits and upper 8 bits in order.
The TB0RG0 timer register has a double-buffer structure, which is paired with
register buffer. The value set in TB0RUN<TB0RDE> determines whether the
double-buffer structure is enabled or disabled: it is disabled when <TB0RDE> = 0, and
enabled when <TB0RDE> = 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when the values in the up counter (UC0) and the timer register TB0RG1
match.
After a reset, TB0RG0 and TB0RG1 are undefined. If the 16-bit timer is to be used
after a reset, data should be written to it beforehand.
On a reset TB0RUN<TB0RDE> is initialized to 0, disabling the double buffer. To use
the double buffer, write data to the timer register, set <TB0RDE> to 1, then write data
to the register buffer as shown below.
TB0RG0 and the register buffer both have the same memory addresses (000188H
and 000189H) allocated to them. If <TB0RDE> = 0, the value is written to both the
timer register and the register buffer. If <TB0RDE> = 1, the value is written to the
register buffer only.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0
Upper 8 bits
(TB0RG0H)
000189H
The timer registers are write-only registers and thus cannot be read.
(4) Capture registers (TB0CP0H/L and TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counter UC0.
Data in the capture registers should be read all 16 bits. For example, using a 2-byte
data load instruction or two 1-byte data load instructions. The least significant byte is
read first, followed by the most significant byte.
The addresses of the capture registers are as follows:
TMRB0
TB0CP0
Upper 8 bits
(TB0CP0H)
00018DH
The capture registers are read-only registers and thus cannot be written to.
Lower 8 bits Upper 8 bits
(TB0RG0L) (TB0RG1H)
000188H 00018BH
Lower 8 bits Upper 8 bits
(TB0CP0L) (TB0CP1H)
00018CH 00018FH
91C829-106
TMP91C829
TB0RG1
Lower 8 bits
(TB0RG1L)
00018AH
TB0CP1
Lower 8 bits
(TB0CP1L)
00018EH
2006-03-15