Toshiba TLCS-900/L1 Series Manual page 139

b. Receiving
In SCLK output mode the synchronous clock is output on the SCLK0 pin and
the data is shifted to receiving buffer 1. This is initiated when the receive
interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit
data is received, the data is transferred to receiving buffer 2 (SC0BUF) following
the timing shown below and INTES0<IRX0C> is set to 1 again, causing an
INTRX0 interrupt to be generated.
Setting SC0MOD0<RXE>to 1 initiates SCLK0 output.
IRX0C
(INTRX0
interrupt request)
SCLK0 output
(<SCLKS>=0
Rising edge mode)
SCLK0 output
(<SCLKS>=1
Fallingf edge mode)
RXD0
Figure 3.10.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode)
In SCLK input mode the data is shifted to receiving buffer 1 when the SCLK
input goes active. The SCLK input goes active when the receive interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is
received, the data is shifted to receiving buffer 2 (SC0BUF) following the timing
shown below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt
to be generated.
SCLK0 input
(<SCLKS> = 0:
Rising edge mode)
SCLK0 input
(<SCLKS> = 1:
Falling edge mode)
RXD0
IRX0C
(INTRX0 )
Figure 3.10.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode)
Note: The system must be put in the receive enable state (SCMOD0<RXE> = 1) before data can
be received.
Bit0 Bit1
(Channel 0)
Bit0 Bit1
(Channel 0)
91C829-137
Bit6
Bit5 Bit6
TMP91C829
Bit7
Bit7
2006-03-15