Pinning Assignments - Arrow CYC5000 User Manual

5.2.11.4 Ensure that the file is added to the Project: Assignments → Settings and select "Timing
Analyzer". The top.sdc should have been already added by default. If it is not, it will need
to be added manually.

5.2.12 Pinning Assignments

Before the design can be downloaded to the FPGA, pin assignments that match the hardware on
the board are needed. There are different ways to do this such as the Pin Planner, Assignment
Editor, and text files.
The following steps will show one of these ways, the Pin Planner. Since there are only 10 pins that
need to be assigned, the Pin Planner can be used. If many pins are needed, other ways can be used
such as the Quartus Assignment Editor, or by importing constraints from a text file or
spreadsheet.
5.2.12.1 Open the Pin Planner: Assignments → Pin Planner.
CYC5000 User Guide
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March 2023