Peripherals Connected To The Fpga; Communication And Configuration; Figure 4 - Cyc5000 Clock Tree - Arrow CYC5000 User Manual

Board
FPGA Pin No.
Reference
CLK12M PIN_F14
REFCLK PIN_G14
3.3

Peripherals Connected to the FPGA

3.3.1 Communication and Configuration

The CYC5000 board uses a single chip to perform configuration of the device and communication
over USB.
3.3.1.1 USB Communication
The FTDI chip converts signals from USB 2.0 to a variety of standard serial and parallel interfaces.
Channel A of FTDI chip is used in MPPSE mode for JTAG. Channel B is routed to FPGA and is
usable for other standard interfaces.
CYC5000 User Guide
Figure 4 – CYC5000 Clock Tree
Pin Func.
Input 12MHz clock input
Input Optional clock input
Page | 11
Description
www.arrow.com
I/O Std
3.3 V
3.3 V
March 2023