Implementation Results
Figure 4-10
shows the cycle time to be about 417 µs when captured on a logic analyzer which is, well within the
-1% to +10% range allowed by the standard and a passing test result. The answer time of the connected device
can also be seen in this plot.
30
BOOSTXL-IOLINKM-8 EVM User's Guide
Figure 4-9. CQ Line Communication
Figure 4-10. Master Cycle Timing
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SLLU357 – MAY 2023
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