Memory Subsystem Architecture - xFusion Digital Technologies FusionServer CH242 V5 Manual

FusionServer CH242 V5 Compute Node
Technical White Paper
Figure 5-6 Memory identifier
Callout
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5.3.1.2 Memory Subsystem Architecture

The CH242 V5 provides 48 memory slots. Each processor integrates six memory channels.
2022-08-12
Description
Capacity of the memory module
Number of ranks of the memory
module
Data width on the DRAM
Type of the memory interface
Maximum memory speed
Column Access Strobe (CAS)
latency
DIMM type
5 Hardware Description
Definition
⚫ 8 GB
⚫
16 GB
⚫ 32 GB
⚫ 64 GB
⚫ 128 GB
⚫ 1R: single-rank
⚫
2R: dual-rank
⚫ 4R: quad-rank
⚫
8R: octal-rank
⚫ X4: 4-bit
⚫
X8: 8-bit
⚫ PC3: DDR3
⚫
PC4: DDR4
⚫ 2133 MT/S
⚫ 2400 MT/S
⚫ 2666 MT/S
⚫ 2933 MT/S
⚫ P: 15
⚫ T: 17
⚫
R: RDIMM
⚫ L: LRDIMM
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