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IDT Installation of the EB12T3G2 Eval Board
Notes
EB12T3G2 Eval Board Manual
PCI Express Analog High Power Voltage Converter
A DC-DC converter (U18) provides a 2.5V PCI Express analog high power voltage (shown as VDDHA)
to the PES12T3G2.
PCI Express Analog Power Voltage Converter
A separate DC-DC converter (U16) provides a 1.0V PCI Express analog power voltage (VDDA) to the
PES12T3G2.
PCI Express Transmitter Analog Power Voltage Converter
A separate DC-DC converter (U17) provides a 1.0V PCI Express transmitter analog power voltage
(shown as VDDPETA) to the PES12T3G2.
Core Logic Voltage Converter
A separate DC-DC converter (U15) provides the 1.0V core voltage (VDDCORE) to the PES12T3G2.
3.3V I/O Voltage Regulator
A 12V to 3.3V voltage regulator (VR1) provides the 3.3V I/O voltage (VDDIO) to the PES12T3G2.
Power-up Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There
are no other power-up sequence requirements for the various operating supply voltages.
Required Jumpers
To deliver power to the PES12T3G2 switch, the following jumpers must be shunted: W25, W21, W22,
W23, and W24. These jumpers were implemented so that the power consumption of the PES12T3G2 can
be measured.
Reset
The PES12T3G2 supports two types of reset mechanisms as described in the PCI Express specifica-
tion:
–
Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES12T3G2, and the endpoints.
– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the 89HPES12T3G2
User Manual. The EB12T3G2 evaluation board provides seamless support for Hot Reset.
Pin
Signal
1
+12V
2
GND
3
GND
4
+5V
Table 2.5 External Power Connector - J1
2 - 3
October 3, 2007
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