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Renesas IDT 89EB-LOGAN-19 Manual

Renesas IDT 89EB-LOGAN-19 Manual

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IDT
89EB-LOGAN-19
™
Evaluation Board Manual
(Evaluation Board: 18-692-001)
February 2011
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2011 Integrated Device Technology, Inc.

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Summary of Contents for Renesas IDT 89EB-LOGAN-19

  • Page 1 ® 89EB-LOGAN-19 ™ Evaluation Board Manual (Evaluation Board: 18-692-001) February 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2011 Integrated Device Technology, Inc.
  • Page 2 DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Table of Contents ® Description of the EB-LOGAN-19 Evaluation Board Notes Introduction ............................. 1-1 Board Features ..........................1-2 Hardware ..........................1-2 Software..........................1-2 Other............................1-2 Revision History ..........................1-2 Installation of the EB-LOGAN-19 Evaluation Board EB-LOGAN-19 Installation ......................2-1 PCI Express Mezzanine and Edge Adapters.................. 2-1 Hardware Description ........................
  • Page 4 IDT Table of Contents Notes 89EB-LOGAN-19 Evaluation Board February 16, 2011...
  • Page 5 List of Tables ® Table 2.1 EB-LOGAN-19 Global Clock Select ..................2-4 Notes Table 2.2 Clock Buffer Input Sources ....................2-5 Table 2.3 Global Reference Input Clock Frequency Select ..............2-6 Table 2.4 Onboard Clock Generator Frequency Select ..............2-6 Table 2.5 Onboard Reference Clock Generator Access Points ............
  • Page 6 IDT List of Tables Notes 89EB-LOGAN-19 Evaluation Board February 16, 2011...
  • Page 7 List of Figures ® Figure 1.1 Function Block Diagram of the EB-LOGAN-19 Evaluation Board ........1-1 Notes Figure 2.1 Bifurcated and Merged Mezzanine Cards ................2-1 Figure 2.2 MiniSAS Mezzanine Adapter ....................2-2 Figure 2.3 EB-LOGAN-19 iSAS-to-SATA Breakout Cable ..............2-2 Figure 2.4 PCIe x1 Edge-to-SATA Adapter ..................2-3 Figure 2.5 EB-LOGAN-19 Evaluation Main Board ................2-3 Figure 2.6...
  • Page 8 IDT List of Figures Notes 89EB-LOGAN-19 Evaluation Board February 16, 2011...

  • Page 9: Introduction

    Chapter 1 Description of the EB-LOGAN-19 Evaluation Board ® Introduction Notes The 89HPES24NT24G2 switch is a member of the IDT PCI Express® Inter-Domain Switch family of products. It is a PCIe® Base Specification 2.1 compliant (Gen2) 24-lane, 24-port switch. The EB-LOGAN- 19 Evaluation Board provides an evaluation platform for the PES24NT24G2 switch and for other members of this switch family including PES16NT16G2 and PES12NT12G2.

  • Page 10: Board Features

    IDT Description of the EB-LOGAN-19 Evaluation Board Board Features Notes Hardware PES24NT24G2 PCIe 24-port switch – Twenty four ports (each x1) - for port 8 and higher, adjacent ports may be combined to create x2, x4 or x8 ports – PCIe Base Specification Revision 2.1 compliant (Gen2 SerDes speeds of 5 GT/S) –...
  • Page 11 IDT Description of the EB-LOGAN-19 Evaluation Board Notes April 23, 2010: Updated Schematics in Chapter 4. August 18, 2010: Updated the manual for Rev. 2.0 board February 16, 2011: Changed default settings from Off to On in Tables 2.3 and 2.4. 89EB-LOGAN-19 Evaluation Board 1 - 3 February 16, 2011...
  • Page 12 IDT Description of the EB-LOGAN-19 Evaluation Board Notes 89EB-LOGAN-19 Evaluation Board 1 - 4 February 16, 2011...

  • Page 13: Installation Of The Eb-Logan-19 Evaluation Board

    Chapter 2 Installation of the EB-LOGAN-19 Evaluation Board ® EB-LOGAN-19 Installation Notes This chapter discusses the steps required to configure and install the EB-LOGAN-19 evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1.
  • Page 14 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Pictured in Figure 2.2 is the mini-SAS Mezzanine card which consists of two iSAS and two SATA connectors. Each iSAS connector supports up to PCI Express x4 width and the SATA connectors are used for clock and reset signals of each x4 or less stack/port.

  • Page 15: Hardware Description

    IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Figure 2.4 PCIe x1 Edge-to-SATA Adapter Hardware Description The PES24NT24G2 is a 24-lane, 24-port PCI Express® switch. It is a peripheral chip that performs PCI Express based switching with a feature set optimized for high performance applications such as servers and storage.

  • Page 16: Reference Clocks

    IDT Installation of the EB-LOGAN-19 Evaluation Board Notes 8-P IN EPS 12V 8-P IN EPS 12V 24-PIN ATX 24-PIN ATX +3.3 +3.3 clk[0:11] clk[0:11] 1:12 1:12 On-Board On-Board Clock Gen Clock Gen Buffer Buffer SATA SATA Data Data Data Data Data Data Data...
  • Page 17 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes CONNECTION CONNECTION JMP1 JMP1 JMP2 JMP2 IOA <-> COM IOA <-> COM IOB <-> COM IOB <-> COM IOC <-> COM IOC <-> COM 8-10 8-10 IOD <-> COM IOD <-> COM 9-11 9-11 10-12...

  • Page 18: Local Port Input Clocks

    IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Global Clock Frequency Switch - SW10[2 SW10[2] Clock Frequency 100 MHz (Default) 125 MHz Table 2.3 Global Reference Input Clock Frequency Select The source for the onboard clock is the ICS841484 clock generator device (U49) connected to a 25MHz oscillator (X1).

  • Page 19: Table 2.7 Eb-Logan-23 Port 16 Clock Source Select

    IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Port 16 Clock Source Select - S17[1] S17[1] Clock Source SATA J64 Port 16 Clock Generator (U120) Table 2.7 EB-LOGAN-23 Port 16 Clock Source Select Slot # Header Selection [1-3 / 2-4] Onboard Clock Generator (U118) [3-5 / 4-6] From Clock Buffer [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J35)

  • Page 20: Power Sources

    IDT Installation of the EB-LOGAN-19 Evaluation Board Power Sources Notes Power for the PES24NT24G2 and all downstream ports will be generated from the 12V from an external power connector. See Table 2.10. A 12V to 3.3V DC-DC converter will be used to provide power to five switching regulators to generate V CORE, V PEA, V...

  • Page 21: Heatsink Requirement

    IDT Installation of the EB-LOGAN-19 Evaluation Board Heatsink Requirement Notes The EB-LOGAN-19 evaluation board utilizes a heatsink with integrated fan. Reset The PES24NT24G2 supports two types of reset mechanisms as described in the PCI Express specifica- tion: – Fundamental Reset: This is a system-generated reset that propagates along the PCI Express tree through a single side-band signal PERST# which is connected to the Root Complex, the PES24NT24G2, and the endpoints.

  • Page 22: Boot Configuration Vector

    IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Ports Associated with the Stack Stack Stack 0 0, 1, 2, 3 Stack 1 4, 5, 6, 7 Stack 2 8, 9, 10, 11, 12, 13, 14, 15 Stack 3 16, 17, 18, 19, 20, 21, 22, 23 Table 2.11 Ports in Each Stack Boot Configuration Vector A boot configuration vector consisting of the signals listed in Table 2.12 is sampled by the...

  • Page 23: Smbus Interfaces

    IDT Installation of the EB-LOGAN-19 Evaluation Board SMBus Interfaces Notes The System Management Bus (SMBus) is a two-wire interface through which various system compo- nent chips can communicate. It is based on the principles of operation of I C. Implementation of the SMBus signals in the PCI Express connector is optional and may not be present on the host system.

  • Page 24: Smbus Master Interface

    IDT Installation of the EB-LOGAN-19 Evaluation Board SMBus Master Interface Notes Connected to the master SMBus interface are twenty-two 16-bit I/O Expanders (MAX7311AUG) and a serial EEPROM, U77 (24LC512). The I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B).
  • Page 25 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Side A Side B RSVD Reserved Ground Ground REFCLK+ REFCLK Reference clock PETp0 Transmitter differential REFCLK- (differential pair) PETn0 pair, Lane 0 Ground Ground PERp0 Receiver differential PRSNT2# Hot-Plug presence detect PERn0 pair, Lane 0 Ground Ground...
  • Page 26 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Side A Side B Ground PERp7 Receiver differential PRSNT2# Hot-Plug presence detect PERn7 pair, Lane 7 Ground Ground Table 2.17 PCI Express x8 Connector Pinout (Part 3 of 3) 89EB-LOGAN-19 Evaluation Board 2 - 14 February 16, 2011...

  • Page 27: Eb-Logan-19 Board Figure

    IDT Installation of the EB-LOGAN-19 Evaluation Board EB-LOGAN-19 Board Figure Notes Figure 2.9 EB24NT24G2 Evaluation Board 89EB-LOGAN-19 Evaluation Board 2 - 15 February 16, 2011...
  • Page 28 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes 89EB-LOGAN-19 Evaluation Board 2 - 16 February 16, 2011...

  • Page 29: Software For The Eb-Logan-19 Eval Board

    Chapter 3 Software for the EB-LOGAN-19 Eval Board ® Introduction Notes This chapter discusses some of the main features of the available software to give users a better under- standing of what can be achieved with the EB-LOGAN-19 evaluation board using the device management software.
  • Page 30 IDT Software for the EB-LOGAN-19 Eval Board Notes 89EB-LOGAN-19 Evaluation Board 3 - 2 February 16, 2011...

  • Page 31: Schematics

    Chapter 4 Schematics ® Schematics Notes 89EB-LOGAN-19 Evaluation Board 4 - 1 February 16, 2011...
  • Page 32 REVISIONS DESCRIPTION DATE CHANGE BY INITIAL RELEASE 2009-12-05 T. TRAN TITLE PAGE / TABLE OF CONTENTS SAS CONNECTOR PORTS POWER CONNECTORS, MIN LOAD RESISTORS POWER REGULATOR - VDDIO MEZZANINE CONNECTOR PORTS 8, 12 POWER REGULATOR - VDDCORE MEZZANINE CONNECTOR PORTS 16, 20 POWER REGULATOR - VDDPEA 24NT24G2 - SERDES POWER REGULATOR - VDDPEHA...

  • Page 33: Sas Connector Ports

    MOLEX_IPASS_36 MOLEX_IPASS_36 GND1 GND7 GND1 GND7 PE00RP0 0.1UF PE00TP0 PE04RP0 0.1UF PE04TP0 RX0P TX0P RX0P TX0P PE00RN0 PE00TN0 PE04RN0 PE04TN0 0.1UF 0.1UF RX0N TX0N RX0N TX0N GND2 GND8 GND2 GND8 PE01RP0 0.1UF PE01TP0 PE05RP0 0.1UF PE05TP0 RX1P TX1P RX1P TX1P PE01RN0 PE01TN0 PE05RN0...

  • Page 34: Mezzanine Connector Ports 8/12

    S8_3VAUX S12_3VAUX S8_12V S8_3V S12_12V S12_3V 470-1075-600 (1 of 2) 470-1075-600 (2 of 2) Wafer 0 Wafer 5 PE15TN0 PE10TN0 PE15TP0 PE10TP0 PE15RN0 PE10RN0 PE15RP0 PE10RP0 P12_PDN STK2CFG1 Wafer 1 Wafer 6 PE09TN0 PE14TN0 PE14TP0 PE09TP0 PE14RN0 PE09RN0 PE14RP0 PE09RP0 STK2CFG1 &...
  • Page 35 S16_3VAUX S20_3VAUX S16_12V S16_3V S20_12V S20_3V 470-1075-600 (1 of 2) 470-1075-600 (2 of 2) Wafer 0 Wafer 5 PE23TN0 PE18TN0 PE23TP0 PE18TP0 PE23RN0 PE18RN0 PE23RP0 PE18RP0 P20_PDN STK3CFG1 Wafer 1 Wafer 6 PE22TN0 PE17TN0 PE22TP0 PE17TP0 PE22RN0 PE17RN0 PE22RP0 PE17RP0 STK3CFG1 &...

  • Page 36: 24Nt24G2 - Serdes

    89HPES24NT24G2 (3/8) 89HPES24NT24G2 (5/8) PE00RP0 PE00TP0 PE16RP0 PE16TP0 PE00RP0 PE00TP0 PE16RP0 PE16TP0 PE00RN0 PE00TN0 PE16RN0 PE16TN0 PE00RN0 PE00TN0 PE16RN0 PE16TN0 PE01RP0 PE01TP0 PE17RP0 PE17TP0 PE01RP0 PE01TP0 PE17RP0 PE17TP0 PE01RN0 PE01TN0 PE17RN0 PE17TN0 PE01RN0 PE01TN0 PE17RN0 PE17TN0 PE02RP0 PE02TP0 PE18RP0 PE18TP0 PE02RP0 PE02TP0 PE18RP0...

  • Page 37: 24Nt24G2 - Clk, Config, Gpio

    89HPES24NT24G2 (1/8) P08CLKP GCLK0P GCLKP0 P08CLKP GCLK0N P08CLKN GCLKN0 P08CLKN P16CLKP GCLK1P GCLKP1 P16CLKP GCLK1N P16CLKN GCLKN1 P16CLKN DUT RESET GCLKFSEL GCLKFSEL HDR_2x6 MAIN_RSTN PERSTN PERSTN SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 RSTHALT RSTHALT SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 STK2CFG0 STK2CFG0 STK2CFG1 STK2CFG1 TP108 STK2CFG2 J118 STK2CFG2 STK2CFG3 STK2CFG3 STK2CFG4...
  • Page 38 +1V0_CORE CP10 +12V3_PS +5V0_PS LABEL: FAN LABEL: 0.1UF 0.1UF 0.1UF 0.1UF 12V/5V +1V0_PEA +1V0_CORE +3V3_IO 89HPES24NT24G2 (8/8) VSS1 VSS44 0.1UF 0.1UF 0.1UF 0.1UF VSS2 VSS45 89HPES24NT24G2 (6/8) VSS3 VSS46 VDDCORE1 VDDIO1 VSS4 VSS47 VDDCORE2 VDDIO2 VSS5 VSS48 VDDCORE3 VDDIO3 VSS6 VSS49 VDDCORE4 VDDIO4...

  • Page 39: Ioexpander

    +3V3 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD MAX7311AUG +3V3 MAX7311AUG PLACE RESISTORS ON CLOSE AND P0_APN P2_APN ON SAME SIDE OF BOARD P0_PDN P2_PDN P0_PFN P2_PFN P0_PWRGDN P2_PWRGDN 2.7K P0_AIN P2_AIN P0_PIN P2_PIN P0_PEP P2_PEP P0_RSTN P2_RSTN P4_APN...

  • Page 40: Ioexpander

    +3V3 +3V3 PLACE RESISTORS ON CLOSE AND PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD ON SAME SIDE OF BOARD +3V3 +3V3 MAX7311AUG MAX7311AUG P1_APN P10_APN P1_PDN P10_PDN P1_PFN P10_PFN P1_PWRGDN P10_PWRGDN 2.7K 2.7K P1_AIN 2.7K P10_AIN P1_PIN P10_PIN P1_PEP P10_PEP...

  • Page 41: Ioexpander

    +3V3 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD +3V3 PLACE RESISTORS ON CLOSE AND MAX7311AUG MAX7311AUG ON SAME SIDE OF BOARD P9_APN P17_APN P9_PDN P17_PDN R107 R119 P9_PFN P17_PFN R108 P9_PWRGDN R120 P17_PWRGDN 2.7K R109 P9_AIN R121 P17_AIN P9_PIN...

  • Page 42: Ioexpander

    +3V3 +3V3 PLACE RESISTORS ON CLOSE AND PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD ON SAME SIDE OF BOARD +3V3 +3V3 MAX7311AUG MAX7311AUG P0_MRLN P0_ILOCKST P1_MRLN P2_ILOCKST R1148 R1160 P2_MRLN P4_ILOCKST R1149 P3_MRLN R1161 P6_ILOCKST 2.7K 2.7K R1150 P4_MRLN 2.7K...

  • Page 43: Ioexpander

    +3V3 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD PLACE RESISTORS ON CLOSE AND MAX7311AUG MAX7311AUG ON SAME SIDE OF BOARD P9_ILOCKST P0_ACTIVEN P11_ILOCKST P1_ACTIVEN R1124 R1136 P13_ILOCKST P2_ACTIVEN R1125 P15_ILOCKST R1137 P3_ACTIVEN R1126 P17_ILOCKST R1138 P4_ACTIVEN P19_ILOCKST P5_ACTIVEN P21_ILOCKST...

  • Page 44: Ioexpander

    +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD MAX7311AUG P0_RSTN P2_RSTN R131 P4_RSTN R132 P6_RSTN R133 P8_RSTN P12_RSTN P16_RSTN P20_RSTN PART0_PERSTN MSMBCLK R137 PART1_PERSTN MSMBDAT R138 PART2_PERSTN PART3_PERSTN PART4_PERSTN PART5_PERSTN PART6_PERSTN PART7_PERSTN R1633 IOEXPINTN INT_N IOEXPANDER 20 ADDR: 0XA8 +3V3 PLACE RESISTORS ON CLOSE AND...

  • Page 45: Hot Plug Control Ports

    +3V3_PS +12V3_PS +3V3_PS S8_3V 0.008 R246 R254 R256 S8_12V R248 0.013 R252 LTC4242CUHF 12VOUT1 3VIN1 12VGATE1 3VSENSE1 S8_3VAUX 12VSENSE1 3VGATE1 12VIN1 3VOUT1 AUXIN1 AUXOUT1 R225 AUXON1 P8_PEP R226 R227 FAULTN1 FON1 P8_PFN R228 AUXFAULTN1 ENN1 R229 AUXPGOODN1 P8_PWRGDN R230 PGOODN1 GND1 R231 FAULTN2...

  • Page 46: Hot Plug Control Ports

    +3V3_PS +12V3_PS +3V3_PS S16_3V 0.008 R281 R289 R291 S16_12V R283 0.013 R287 LTC4242CUHF 12VOUT1 3VIN1 12VGATE1 3VSENSE1 S16_3VAUX 12VSENSE1 3VGATE1 12VIN1 3VOUT1 AUXIN1 AUXOUT1 R260 AUXON1 P16_PEP R261 R262 FAULTN1 FON1 P16_PFN R263 AUXFAULTN1 ENN1 R264 AUXPGOODN1 P16_PWRGDN R265 PGOODN1 GND1 R266 FAULTN2...

  • Page 47: Slot Resets And Wake Pull-Ups

    +3V3 +3V3 +3V3 +3V3 SN74LVC1G125 SN74LVC1G125 SN74LVC1G125 P23_RSTN P15_RSTN P7_RSTN OE_N OE_N OE_N SLOT_RSTN23 SLOT_RSTN15 SLOT_RSTN7 R1285 SLOT_WAKEN0 R1286 SLOT_WAKEN1 U100 U108 R1287 SLOT_WAKEN2 R1288 SLOT_WAKEN3 SN74LVC1G125 SN74LVC1G125 SN74LVC1G125 P22_RSTN P14_RSTN P6_RSTN OE_N OE_N OE_N R1289 SLOT_WAKEN4 R1290 SLOT_WAKEN5 R1291 SLOT_WAKEN6 R1292 SLOT_RSTN22...

  • Page 48: Clock

    R306 0603 +3V3 22PF C270 120OHM 0805 400MA C271 22PF ICS841484 XTAL_IN XTAL_OUT REF_IN VDDA R301 33.2 REF_SEL REF_OUT ICS_FS 33.2 R302 CGCLKP FSEL0 R307 CGCLKN 33.2 FSEL1 33.2 R303 678005005 33.2 R308 OE_REFOUT R304 33.2 CG_SATA_CLKP MR_nOE R309 CG_SATA_CLKN 33.2 IREF ICS_SSM...

  • Page 49: Clock Buffer

    +3V3 600OHM R333 0805 500MA +3V3 ICS9DB803 678005005 VDDA MAIN_CLKP BGCLK0P_R 33.2 R334 BGCLK0P SRC_IN DIF_0 MAIN_CLKN R335 BGCLK0N_R 33.2 BGCLK0N SRC_IN# DIF_0# 33.2 R336 BGCLK1P OE0# DIF_1 BGCLK1P_R BGCLK1N_R 33.2 R337 BGCLK1N DIF_1# OE1# 33.2 R338 BS08CLKP MTG1 DIF_2 BS08CLKP_R MTG1 BS08CLKN_R...
  • Page 50 P08CLK - DUT PORT 8 CLK LP8CLK - LOCAL CLOCK GEN. PORT 8 CLK P8SHXXCLK - TO SLOT CLK HEADERS +3V3 +3V3 +3V3 +3V3 R501 C136 CLOSE TO VDDA 0603 ICS874001I-02 VDDA VDDO ICS853S1208I P8ECLK_ENABLE P8_OEA0 OEA0 DIV_SELA P8_OEA1 0.1UF C148 P08CLKP F_SEL1...
  • Page 51 P16CLK - DUT PORT 16 CLK LP16CLK - LOCAL CLOCK GEN. PORT 16 CLK P16SHXXCLK - TO SLOT CLK HEADERS +3V3 +3V3 +3V3 +3V3 C85 CLOSE TO VDDA R366 0603 ICS874001I-02 VDDA VDDO ICS853S1208I P16ECLK_ENABLE P16_OEA0 OEA0 DIV_SELA P16_OEA1 0.1UF C117 P16CLKP F_SEL1...
  • Page 52 SXXCLK - SLOT CLK BSXXLCK - BUFFER SLOT CLK LSXXCLK - LOCAL CLOCK GEN. SLOT CLK SHXXCLK - SLOT HDR.CLK 678005005 678005005 S8_SATACLKP S16_SATACLKP S8_SATACLKN S16_SATACLKN HDR_2x6 HDR_2x6 LS8_CLKP LS8_CLKN P8SH16_CLKP P8SH16_CLKN S8_CLKP S8_CLKN S8_SATA_RSTN S16_CLKP S16_CLKN S16_SATA_RSTN BS08CLKP S8_SATA_WAKE BS16CLKP S16_SATA_WAKE BS08CLKN...
  • Page 53 MINIMUM POWER SUPPLY LOADS MMBT3904 R506 0603 +12V3_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS SPDT_TGL PS_ENABLEN +12V3_PS MTG1 MTG2 +5V0_PS +5V0_PS +3V3_PS +3V3_PS 0039291247 +3.3V_1 +3.3V_4 +3.3V_2 -12V_1 GND_1 GND_4 +5V_1 PS-ON GND_2 GND_5 +5V_2 GND_6 GND_3 GND_7 PWROK +5VAB +5V_3 +12V3_1 +5V_4 +12V3_2...
  • Page 54 +12V3_PS +3V3 VDD_IO, 3.3V CONN BANANA LTM4603 VIN1 VOUT1 VIN2 VOUT2 VIN3 VOUT3 VIN4 VOUT4 VIN5 VOUT5 VIN6 VOUT6 CONN BANANA VIN7 VOUT7 VIN8 VOUT8 VIN9 VOUT9 VIN10 VOUT10 VIN11 VOUT11 VIN12 VOUT12 VIN13 VOUT13 VIN14 VOUT14 VIN15 VOUT15 +3V3_IO VIN16 VOUT16 VIN17...
  • Page 55 +12V3_PS VDD_CORE, 1.0V +3V3 +3V3 CONN BANANA DS117 J114 LTM4603 VIN1 VOUT1 VIN2 VOUT2 VIN3 VOUT3 CONN BANANA MMBT3904 VIN4 VOUT4 J113 VIN5 VOUT5 VIN6 VOUT6 VIN7 VOUT7 VIN8 VOUT8 VIN9 VOUT9 VIN10 VOUT10 VIN11 VOUT11 VIN12 VOUT12 VIN13 VOUT13 VIN14 VOUT14 VIN15...
  • Page 56 +12V3_PS VDD_PEA, 1.0V +3V3 +3V3 CONN BANANA DS133 J115 LTM4603 VIN1 VOUT1 VIN2 VOUT2 VIN3 VOUT3 MMBT3904 VIN4 VOUT4 VIN5 VOUT5 VIN6 VOUT6 VIN7 VOUT7 VIN8 VOUT8 VIN9 VOUT9 VIN10 VOUT10 VIN11 VOUT11 VIN12 VOUT12 VIN13 VOUT13 VIN14 VOUT14 VIN15 VOUT15 +1V0_PEA VIN16...
  • Page 57 +12V3_PS VDD_PEHA, 2.5V +3V3 +3V3 CONN BANANA DS134 J116 LTM4603 VIN1 VOUT1 VIN2 VOUT2 VIN3 VOUT3 MMBT3904 VIN4 VOUT4 VIN5 VOUT5 VIN6 VOUT6 VIN7 VOUT7 VIN8 VOUT8 VIN9 VOUT9 VIN10 VOUT10 VIN11 VOUT11 VIN12 VOUT12 VIN13 VOUT13 VIN14 VOUT14 VIN15 VOUT15 +2V5_PEHA VIN16...
  • Page 58 +12V3_PS VDD_PETA, 1.0V +3V3 +3V3 CONN BANANA DS135 J117 LTM4603 VIN1 VOUT1 VIN2 VOUT2 VIN3 VOUT3 MMBT3904 VIN4 VOUT4 VIN5 VOUT5 VIN6 VOUT6 VIN7 VOUT7 VIN8 VOUT8 VIN9 VOUT9 VIN10 VOUT10 VIN11 VOUT11 VIN12 VOUT12 VIN13 VOUT13 VIN14 VOUT14 VIN15 VOUT15 +1V0_PETA VIN16...
  • Page 59 +3V3 +3V3 +3V3 +3V3 +3V3 SN74LVC1G125 +3V3 SATAIN_RSTN OE_N TLC7733D RESINN R644 SENSE RESET MAIN_RSTN 0603 CONTROL RESETN FUNDAMENTAL RESET SPDT_MOM MOMSW_RSTN MTG1 MTG2 +3V3 +3V3 +3V3 BOOT EEPROM SOCKETED (52-298-000) +3V3 JTAG HDR_2x7 DUT_JTAG_TRST_N DUT_JTAG_TDI DUT_JTAG_TDO 24LC512 DUT_JTAG_TMS MSMBCLK DUT_JTAG_TCK MSMBDAT VERT-TH...
  • Page 60 +3V3 (GREEN) ACTIVE HIGH - DIP STK2CFG STK2CFG4 R796 DS102 STK2CFG STK2CFG3 R797 DS103 DIPSW8 STK2CFG2 R798 DS104 STK2CFG0 STK2CFG1 STK2CFG1 R799 DS105 STK2CFG2 R800 DS106 STK2CFG3 STK2CFG0 STK2CFG4 +3V3 SPARE1 TP106 SPARE2 SPARE3 +3V3 (GREEN) ACTIVE HIGH - DIP STK3CFG DIPSW8 ICS_FS GCLKFSEL...
  • Page 61 +3V3 (YELLOW) ACTIVE LOW - GPIO GPIO ALT0 ALT1 ----------------------------------- R1368 DS406 GPIO0 | PART0PERSTN | P16LINKUPN ----------------------------------- GPIO1 R1369 DS407 | PART1PERSTN | P16ACTIVEN ----------------------------------- GPIO2 R1370 DS408 | PART2PERSTN | P4LINKUPN ----------------------------------- GPIO3 R1371 DS409 | PART3PERSTN | P4ACTIVEN TP19 ----------------------------------- GPIO4...
  • Page 62 +3V3 +3V3 (RED) ACTIVE LOW - POWER FAULT (GREEN) ACTIVE LOW - POWER GOOD P23_PFN P23_PWRGDN R663 PORT 23 R687 DS29 PORT 23 P22_PFN P22_PWRGDN R664 R688 DS30 PORT 22 PORT 22 P21_PFN R665 P21_PWRGDN R689 DS31 PORT 21 PORT 21 P20_PFN P20_PWRGDN R666...
  • Page 63 +3V3 +3V3 (ORANGE) ACTIVE LOW - ATTENTION OUTPUT (GREEN) ACTIVE LOW - POWER INDICATOR P23_AIN P23_PIN R900 DS206 PORT 23 R924 DS230 PORT 23 P22_AIN P22_PIN R901 DS207 R925 DS231 PORT 22 PORT 22 P21_AIN R902 DS208 P21_PIN R926 DS232 PORT 21 PORT 21 P20_AIN...
  • Page 64 +3V3 (GREEN) ACTIVE HIGH - POWER ENABLE (RED) ACTIVE LOW - HP SLOT RST P23_PEP P23_RSTN R711 DS53 PORT 23 R735 DS77 PORT 23 P22_PEP P22_RSTN R712 DS54 R736 DS78 PORT 22 PORT 22 P21_PEP R713 DS55 P21_RSTN R737 DS79 PORT 21 PORT 21 P20_PEP...
  • Page 65 +3V3 (GREEN) ACTIVE HIGH - INTERLOCK INPUT (RED) ACTIVE LOW - MRL P23_ILOCKST P23_MRLN R948 DS254 PORT 23 R972 DS278 PORT 23 P22_ILOCKST R949 DS255 P22_MRLN R973 DS279 PORT 22 PORT 22 P21_ILOCKST R950 DS256 P21_MRLN R974 DS280 PORT 21 PORT 21 P20_ILOCKST P20_MRLN...
  • Page 66 +3V3 +3V3 (RED) ACTIVE LOW - PARTITION FUND. RESET (RED) ACTIVE LOW - SLOT HEADER RESET PART7_PERSTN R1020 DS326 SLOT_HDR_RSTN20 R1650 DS415 PART 7 SLOT 20 PART6_PERSTN SLOT_HDR_RSTN16 R1021 DS327 PART 6 R1651 DS416 SLOT 16 PART5_PERSTN SLOT_HDR_RSTN12 R1022 DS328 R1652 DS417 PART 5...
  • Page 67 +3V3 +3V3 (GREEN) ACTIVE LOW - LINK UP (BLUE) ACTIVE LOW - LINK ACTIVITY P23_LINKUPN P23_ACTIVEN R1172 DS334 PORT 23 549R R1196 DS358 BLUE PORT 23 P22_LINKUPN P22_ACTIVEN R1173 DS335 549R R1197 DS359 BLUE PORT 22 PORT 22 P21_LINKUPN R1174 DS336 P21_ACTIVEN R1198...
  • Page 68 HDR_2x30 HDR_2x30 HDR_2x30 R1220 SLOT_RSTN8 R1240 SLOT_RSTN12 R1260 SLOT_RSTN4 P8_PDN P12_PDN P4_PDN R1221 SLOT_WAKEN8 R1241 SLOT_WAKEN12 R1261 SLOT_WAKEN4 P8_PWRGDN P12_PWRGDN P4_PWRGDN P8_PFN P12_PFN P4_PFN P8_PEP P12_PEP P4_PEP P8_CLK_EN P12_CLK_EN P4_CLK_EN SLOT_RESETN R1222 SLOT_RSTN9 R1242 SLOT_RSTN13 R1262 SLOT_RSTN5 P9_PDN P13_PDN P5_PDN CARD_PRESENTN R1223 SLOT_WAKEN9...
  • Page 69 HDR_2x10 HDR_2x10 PART0_PERSTN PART4_PERSTN SLOT_RSTN0 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN4 SLOT_RSTN6 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_HDR_RSTN20 SLOT_RSTN1 SLOT_RSTN14 SLOT_RSTN3 SLOT_RSTN15 VERT_SM 2.0MM VERT_SM 2.0MM NO-SHROUD NO-SHROUD TP135 TP143 TP136 TP144 HDR_2x10 HDR_2x10 PART1_PERSTN PART5_PERSTN SLOT_RSTN0 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN2 SLOT_RSTN4...
  • Page 70 NOTE: DNP JUMPERS WHEN IOEXPANDER IS ENABLED HDR_2x12 MAIN_RSTN SLOT_RSTN0 SLOT_RSTN1 SLOT_RSTN2 HDR_2x6 SLOT_HDR_RSTN8 SLOT_RSTN3 MAIN_RSTN SLOT_RSTN4 SLOT_RSTN8 SLOT_RSTN5 P16_SATARSTN SLOT_RSTN6 SLOT_HDR_RSTN12 SLOT_RSTN7 SLOT_HDR_RSTN20 SLOT_RSTN8 S8_SATA_RSTN SLOT_RSTN9 J129 VERT-TH 2.54MM NO-SHROUD SLOT_RSTN10 SLOT_RSTN11 VERT J133 2.54MM HDR_2x12 SLOT_RSTN12 SLOT_RSTN13 SLOT_RSTN14 HDR_2x6 SLOT_HDR_RSTN12 SLOT_RSTN15...
  • Page 71 +3V3 R1471 0603 120OHM FB12 0805 400MA 22PF C692 22PF C693 ICS841484 XTAL_IN XTAL_OUT REF_IN VDDA R1466 33.2 REF_SEL REF_OUT TP99 P8_ICS_FSEL0 33.2 R1467 LP8_CLKP FSEL0 R1472 33.2 LP8_CLKN FSEL1 33.2 R1468 678005005 LS8_CLKP 33.2 R1473 LS8_CLKN OE_REFOUT R1469 P8_ICS_MR 33.2 LSATA8_CLKP MR_nOE...
  • Page 72 +3V3 R1519 0603 120OHM FB14 0805 400MA 22PF C714 22PF C715 ICS841484 XTAL_IN XTAL_OUT REF_IN VDDA R1514 33.2 REF_SEL REF_OUT TP101 33.2 R1515 P16_ICS_FSEL0 LP16_CLKP FSEL0 33.2 R1520 LP16_CLKN FSEL1 R1516 678005005 33.2 LS16_CLKP 33.2 R1521 LS16_CLKN OE_REFOUT P16_ICS_MR 33.2 R1517 LSATA16_CLKP MR_nOE...

  • Page 73: Contact Information

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