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Notes
EB12T3G2 Eval Board Manual
Installation of the EB12T3G2
®
EB12T3G2 Installation
This chapter discusses the steps required to configure and install the EB12T3G2 evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Insert the evaluation board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB12T3G2 board is shipped with all jumpers and switches configured to their default settings. In
most cases, the board does not require further modification or setup.
Hardware Description
The PES12T3G2 is a 12-lane, 3-port PCI Express® switch. It is a peripheral chip that performs PCI
Express based switching with a feature set optimized for high performance applications such as servers
and storage. It provides fan-out and switching functions between a PCI Express upstream port and 2 down-
stream ports or peer-to-peer switching between downstream ports.
The EB12T3G2 has two PCI Express downstream ports, accessible through two x16 connectors. All two
ports are capable of negotiating a x1, x2, or x4 link width. All endpoint cards connected to the PES12T3G2
must support at least one of these link widths.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting x4 configuration through a PCI Express
x4 slot.
– x1, x2, or x4 PCI Express Endpoint Cards.
Reference Clocks
The PES12T3G2 requires a differential reference clock. The EB12T3G2 derives this clocks from a
common source which is user-selectable. The common source can be either the host system's reference
clock or the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1.
Clock Configuration Stuffing Option
W6 and W7
Pins 2 and 3
Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2
Upstream Reference Clock – Host system provides clock (Default)
The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB12T3G2 allows selection between multiple
clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.
Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak
energy over a wider bandwidth.
Clock Source
Table 2.1 Clock Source Selection
2 - 1
Chapter 2
Eval Board
October 3, 2007
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