Renesas IDT 89EBPES16T7 Manual
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Renesas IDT 89EBPES16T7 Manual

Renesas IDT 89EBPES16T7 Manual

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®
IDT
89EBPES16T7
™
Evaluation Board Manual
(Eval Board: 18-610-000)
March 2007
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2007 Integrated Device Technology, Inc.

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Summary of Contents for Renesas IDT 89EBPES16T7

  • Page 1 ® 89EBPES16T7 ™ Evaluation Board Manual (Eval Board: 18-610-000) March 2007 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2007 Integrated Device Technology, Inc.
  • Page 2 DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Table of Contents ® Description of the EB16T7 Eval Board Notes Introduction .............................1-1 Board Features ..........................1-2 Hardware ..........................1-2 Software..........................1-2 Other............................1-2 Revision History ..........................1-2 Installation of the EB16T7 Eval Board EB16T7 Installation......................... 2-1 Hardware Description ........................2-1 Host System ...........................
  • Page 4 IDT Table of Contents Notes EB16T7 Eval Board Manual March 30, 2007...
  • Page 5 List of Tables ® Table 2.1 Clock Source Selection .......................2-2 Notes Table 2.2 Clock Frequency Selection ....................2-3 Table 2.3 Clock Spread Spectrum Selection ..................2-3 Table 2.4 SMA Connectors - Onboard Reference Clock ..............2-3 Table 2.5 External Power Connector - J1 ................... 2-4 Table 2.6 Downstream Reset Selection .....................
  • Page 6 IDT Table of Contents Notes EB16T7 Eval Board Manual March 30, 2007...
  • Page 7 List of Figures ® Figure 1.1 Function Block Diagram of the EB16T7 Eval Board ............1-1 Notes Figure 2.1 SuperMicro X6DH8-G2 Motherboard .................2-2 EB16T7 Eval Board Manual March 30, 2007...
  • Page 8 IDT List of Figures Notes EB16T7 Eval Board Manual March 30, 2007...

  • Page 9: Introduction

    Chapter 1 Description of the EB16T7 Eval Board ® Introduction Notes The 89HPES16T7 switch (also referred to as PES16T7 in this manual) is a member of the IDT PCI Express® standard (PCIe®) based line of products. It is a 16-lane, 7-port switch, with 4 serial lanes on three ports and 1 serial lane on four ports.

  • Page 10: Board Features

    IDT Description of the EB16T7 Eval Board Board Features Notes Hardware PES16T7 PCIe 7 port switch – One x8 port, one x4 port, four x1 ports, 16 PCIe lanes – PCIe Base Specification Revision 1.1 compliant – 8 GBps (64Gbps) aggregate switching capacity –...

  • Page 11: Revision History

    IDT Description of the EB16T7 Eval Board Revision History Notes October 19, 2006: Initial publication of board manual. November 13, 2006: In Tables 2.7 and 2.8, changed MSMSDDR to MSMBADDR and removed refer- ences to P23MERGEN, P45MERGEN, and SWMODE[3]. March 30, 2007: In Figure 1.1, revised diagram to show a x4 connection from the PES16T7 device to the x4 downstream slot.
  • Page 12 IDT Description of the EB16T7 Eval Board Notes EB16T7 Eval Board Manual 1 - 4 March 30, 2007...

  • Page 13: Installation Of The Eb16T7 Eval Board

    Chapter 2 Installation of the EB16T7 Eval Board ® EB16T7 Installation Notes This chapter discusses the steps required to configure and install the EB16T7 evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1.

  • Page 14: Reference Clocks

    IDT Installation of the EB16T7 Eval Board Notes Figure 2.1 SuperMicro X6DH8-G2 Motherboard Reference Clocks The PES16T7 requires two differential reference clocks. The EB16T7 derives both of these clocks from a common source which is user-selectable. The common source can be either the host system’s reference clock or the onboard clock generator.

  • Page 15: Power Sources

    IDT Installation of the EB16T7 Eval Board Notes The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz oscillator (Y1). When using the onboard clock generator, the EB16T7 allows selection between multiple clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively. Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak energy over a wider bandwidth.

  • Page 16: Pci Express Serial Data Transmit Termination Voltage Converter

    IDT Installation of the EB16T7 Eval Board Notes Signal +12V Table 2.5 External Power Connector - J1 PCI Express Serial Data Transmit Termination Voltage Converter A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown as VTTPE or VPETVTT) to the PES16T7.

  • Page 17: Fundamental Reset

    IDT Installation of the EB16T7 Eval Board Fundamental Reset Notes There are two types of Fundamental Resets which may occur on the EB16T7 evaluation board: – Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI Express Reset (PERSTN) input pin of the PES16T7.

  • Page 18: Table 2.7 Boot Configuration Vector Signals

    IDT Installation of the EB16T7 Eval Board Notes Signal Description CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices. This pin is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports.

  • Page 19: Smbus Interfaces

    IDT Installation of the EB16T7 Eval Board Notes Signal Description Default S6[8] RSTHALT S5[1] SWMODE[0] S5[2] SWMODE[1] S5[3] SWMODE[2] S5[4] Not Used S5[5] REFCLKM S5[6] MSMBADDR[0] S5[7] MSMBADDR[1] S5[8] MSMBADDR[2] Table 2.8 Boot Configuration Vector Switches S5 & S6 (ON=0, OFF=1) (Part 2 of 2) SMBus Interfaces The System Management Bus (SMBus) is a two-wire interface through which various system compo- nent chips can communicate.

  • Page 20: Table 2.10 Smbus Slave Interface Address Configuration

    IDT Installation of the EB16T7 Eval Board Notes Slave Interface Address Configuration Address Bit Signal SSMBUSADDR[1] SSMBUSADDR[2] SSMBUSADDR[3] SSMBUSADDR[5] Table 2.10 SMBus Slave Interface Address Configuration SMBUS Slave Interface Address Setting Slave Interface SSMBADDR[5] SSMBADDR[3] SSMBADDR[2] SSMBADDR[1] Bus Address 0b1110111 (Default) 0b1110110 0b1110101 0b1110100...

  • Page 21: Smbus Master Interface

    IDT Installation of the EB16T7 Eval Board SMBus Master Interface Notes Connected to the master SMBus interface are four 16-bit I/O Expanders (PCA9555) and a serial EEPROM (24LC512). Four I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B).

  • Page 22: Jtag Header

    IDT Installation of the EB16T7 Eval Board Notes I/O Expander 2 Bus Address 0b0100101 0b0100110 0b0100111 Table 2.14 I/O Expander 2 Bus Address (Part 2 of 2) I/O Expander 4 Bus Address 0b0100100 (Default) 0b0100000 0b0100001 0b0100010 0b0100011 0b0100101 0b0100110 0b0100111 Table 2.15 I/O Expander 4 Bus Address The bus address for the selected EEPROM device is 0b1000 by default and is configurable using...

  • Page 23: Attention Buttons

    IDT Installation of the EB16T7 Eval Board Notes JTAG Connector J4 Signal Direction Signal Direction /TRST - Test reset Input — TDI - Test data Input — TDO - Test data Output — TMS - Test mode select Input — TCK - Test clock Input —...

  • Page 24: Leds

    IDT Installation of the EB16T7 Eval Board Notes Miscellaneous Jumpers, Headers Ref. Type Default Description Designator Header Shunted Bypass hot-plug controller - Enables direct power (+12V and +3.3V) to Ports 4 (Default) Header Shunted Bypass hot-plug controller - Enables direct power (+12V and +3.3V) to Ports 3 (Default) Header Shunted...

  • Page 25: Table 2.20 Led Indicators

    IDT Installation of the EB16T7 Eval Board Notes Location Color Definition DS11 Green Port 6: Power-is-good indicator DS 12 Green Port 5: Power-is-good indicator DS15 Green Port 4: Power-is-good indicator DS14 Green Port 3: Power-is-good indicator DS28 Green Port 2: Power-is-good indicator Green Port 6: Power Indicator Yellow...

  • Page 26: Pci Express Connectors

    IDT Installation of the EB16T7 Eval Board PCI Express Connectors Notes Side A Side B +12V 12V power PRSNT1# Hot-Plug presence detect +12V 12V power +12V 12V power RSVD Reserved +12V 12V power Ground Ground SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p SMDAT SMBus Data JTAG...
  • Page 27 IDT Installation of the EB16T7 Eval Board Notes Side A Side B PETn4 pair, Lane 4 Ground Ground PERp4 Receiver differential Ground PERn4 pair, Lane 4 PETp5 Transmitter differential Ground PETn5 pair, Lane 5 Ground Ground PERp5 Receiver differential Ground PERn5 pair, Lane 5 PETp6...

  • Page 28: Locations Of Connectors, Jumpers, And Switches

    IDT Installation of the EB16T7 Eval Board Notes Note: These x16 PCI Express connectors comply with the PCIe specification. However, the downstream ports on the EB16T7 are electronically connected in either a x4 configuration (port 6) or a x1 configuration (ports 2, 3, 4 and 5). According to the PCI Express specification, the PRSNT1# pin should be wired to the farthest available PRSNT2# pin on the connector.

  • Page 29: Software For The Eb16T7 Eval Board

    Chapter 3 Software for the EB16T7 Eval Board ® Introduction Notes This chapter discusses some of the main features of the available software to give users a better under- standing of what can be achieved with the EB16T7 evaluation board using the device management soft- ware.
  • Page 30 IDT Software for the EB16T7 Eval Board Notes EB16T7 Eval Board Manual 3 - 2 March 30, 2007...

  • Page 31: Schematics

    Chapter 4 Schematics ® Schematics Notes EB16T7 Eval Board Manual 4 - 1 March 30, 2007...
  • Page 32 CR-1 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE1 REVISIONS DESCRIPTION DATE CHANGE BY STGC-0082R01 INTIAL RELEASE 2006-08-01 J. CARRILLO SHEET DESCRIPTION TABLE OF CONTENTS BLOCK DIAGRAM POWER SUPPLY AND RESET CLOCKS SMBUS, JTAG, I/O EXPANDER HOT PLUG CONTROL PORT B/C HOT PLUG CONTROL PORT D/E HOT PLUG CONTROL PORT F PORT B CONN AND 16T7 PORTS PORT C CONNECTOR...
  • Page 33 CR-2 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE2 BLOCK DIAGRAM 89EBPES16T7 TITLE BLOCK DIAGRAM SIZE DRAWING FAB P/N REV. STGSCH-00083 18-610-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNILOGY, INC. J.CARRILLO B.OH 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2006 Tue Aug 01 17:54:15 2006 SHEET 2 OF 17...
  • Page 34 CR-3 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE3 3_3V 3_3V 3_3V 3_3V 3_3V POWER INDICATOR PLACE NEAR TOP EDGE LABEL ’POWER’ 3_3V BOARD RESET M_PERSTN PB_SW TLC7733D RESINN SENSE RESET CONTROL RESETN PERST* 3 14 PERST* 3 14 12V_DS 12_0V U/S +12V -> +3.3V 3_3V 12_0V TP16 TP17...
  • Page 35 CR-4 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE4 3_3V PLACE RESISTORS CLOSE TO U9 U_REFCLK+ U_REFCLK- 3_3V 3_3V 3_3V ICS9DB801 VDDA SRC_IN DIF_0 B_REFCLKP SRC_IN# DIF_0# B_REFCLKN 3_3V 0.1UF PB_PWRGDN OE0# DIF_1 M_REFCLK1P 0.1UF DIF_1# M_REFCLK1N SM_SW8 OE1# 0.1UF SSC_S0 DIF_2 M_REFCLK2P SSC_S1 0.1UF OE2# DIF_2# M_REFCLK2N SSC_SS0...
  • Page 36 CR-5 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE5 3_3V 3_3V 3_3V 3_3V 3_3V R102 PDAIN DS10 R103 PLACE EEPROM ON SOCKET 3_3V PDPIN R104 R105 3_3V R106 R107 PFAIN 3_3V R108 PFPIN R109 EEPROM PCA9555 SM_SW8 M_GPIO2 INT# 24LC512 M_SCL M_SWMODE0 M_SCL M_SWMODE1 M_SDA M_SDA M_SWMODE2 PFAPN PDAPN...
  • Page 37 CR-6 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE6 12_0V B_PCIE_3_3AUX 3_3VAUX B_PCIE_3_3AUX 0.02 R141 3_3V PMOSFET 0.022UF B_PCIE_12V R144 6800PF B_PCIE_12V MIC2591B 23.2K R120 IREF VAUXA R121 110K RFTR 12VINA 0.01UF CFTRA 0.01UF CFTRB 12VSNSA FORCE ON 3_3V_DS F_ONA* 12GATEA 3_3V F_ONB* GPI_A0 12VOUTA GPI_B0 3VINA PBPEP AUXENA...
  • Page 38 CR-7 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE7 12V_DS D_PCIE_3_3AUX 3_3VAUX 3_3V D_PCIE_3_3AUX 0.02 R170 PMOSFET D_PCIE_12V 0.022UF R173 6800PF D_PCIE_12V MIC2591B 23.2K R156 IREF VAUXA 110K R155 RFTR 12VINA 0.01UF CFTRA 0.01UF CFTRB 12VSNSA 3_3V_DS FORCE ON F_ONA* 12GATEA F_ONB* GPI_A0 12VOUTA GPI_B0 3VINA PDPEP AUXENA PEPEP...
  • Page 39 CR-8 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE8 12V_DS F_PCIE_3_3AUX 3_3VAUX 3_3V F_PCIE_3_3AUX 0.02 R245 PMOSFET F_PCIE_12V 0.022UF C111 R246 6800PF C110 F_PCIE_12V MIC2591B 23.2K R236 IREF VAUXA 110K R227 RFTR 12VINA 0.01UF CFTRA 0.01UF CFTRB 12VSNSA 3_3V_DS FORCE ON F_ONA* 12GATEA F_ONB* GPI_A0 12VOUTA GPI_B0 3VINA PFPEP...
  • Page 40 CR-9 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE9 B_PCIE_12V B_3_3V 12_0V B_12V B_PCIE_12V B_PCIE_3_3V B_12V 3_3V PCIE_X16_CONN_RA R181 +12V PRSTN1# B_PCIE_3_3V +12V +12V B_3_3V RSVD +12V M_SSMBCLK R179 12 11 10 4 16 SMCLK JTAG2 M_SSMBDATA R180 13 12 11 10 4 16 14 5 SMDAT JTAG3 JTAG4...
  • Page 41 CR-10 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE10 C_PCIE_12V 12V_DS C_12V 3_3V_DS C_PCIE_12V C_PCIE_3_3V C_12V PCIE_CONN_x1 C_3_3V C_PCIE_3_3V R187 +12V PRSTN1# C_3_3V +12V +12V RSVD +12V M_SSMBCLK R185 SMCLK JTAG2 M_SSMBDATA R186 SMDAT JTAG3 JTAG4 C_PCIE_3_3AUX +3.3V JTAG5 JTAG1 +3.3V C_PCIE_3_3AUX 3.3VAUX +3.3V C_WAKE* C_PERST* WAKE# PERST# RSVD...
  • Page 42 CR-11 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE11 D_PCIE_12V 12V_DS D_12V D_PCIE_12V D_12V 3_3V_DS D_PCIE_3_3V PCIE_CONN_x1 D_3_3V R193 +12V PRSTN1# +12V +12V D_PCIE_3_3V RSVD +12V D_3_3V M_SSMBCLK R191 SMCLK JTAG2 M_SSMBDATA R192 SMDAT JTAG3 JTAG4 D_PCIE_3_3AUX +3.3V JTAG5 JTAG1 +3.3V D_PCIE_3_3AUX 3.3VAUX +3.3V D_WAKE* D_PERST* WAKE# PERST# RSVD...
  • Page 43 CR-12 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE12 12V_DS E_PCIE_12V E_3_3V E_12V E_PCIE_12V E_12V PCIE_CONN_x1 E_PCIE_3_3V 3_3V_DS R199 +12V PRSTN1# +12V +12V RSVD +12V E_PCIE_3_3V E_3_3V M_SSMBCLK R197 SMCLK JTAG2 M_SSMBDATA R198 SMDAT JTAG3 JTAG4 E_PCIE_3_3AUX +3.3V JTAG5 JTAG1 +3.3V E_PCIE_3_3AUX 3.3VAUX +3.3V E_WAKE* E_PERST* WAKE# PERST# RSVD...
  • Page 44 CR-13 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE13 12V_DS F_PCIE_12V F_3_3V E_12V F_PCIE_12V E_12V PCIE_CONN_x1 F_PCIE_3_3V 3_3V_DS R252 +12V PRSTN1# +12V +12V RSVD +12V F_PCIE_3_3V F_3_3V M_SSMBCLK R250 SMCLK JTAG2 M_SSMBDATA R251 SMDAT JTAG3 JTAG4 F_PCIE_3_3AUX +3.3V JTAG5 JTAG1 +3.3V F_PCIE_3_3AUX 3.3VAUX +3.3V F_WAKE* F_PERST* WAKE# PERST# RSVD...
  • Page 45 CR-14 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE14 3_3VAUX 12_0V 12_0V PCIE_X8_EDGE C150 +12V PRSTN1# 10UF C148 +12V +12V 6.8UF RSVD +12V R202 M_SSMBCLK SMCLK JTAG_TCK R203 M_SSMBDATA SMDAT JTAG_TDI JTAG_TDO 10UF C149 +3.3V JTAG_TMS C151 JTAG_TRSTN +3.3V 10UF 3.3VAUX +3.3V U_WAKE* PERST* WAKE# PERST# RSVD U_REFCLK+ REFCLK+...
  • Page 46 CR-15 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE15 1_5VA 1_0VA 1_0VC 3_3V VDDPE_J 3_3V_J VDDCORE_J 89HPES16T7ZBBXG JUMPERS MUST BE POPULATED FOR NORMAL OPERATION VSS1 VSS48 VSS2 VSS49 VSS3 VSS50 VSS4 VSS51 VSS5 VSS52 VSS6 VSS53 VSS7 VSS54 VSS8 VSS55 89HPES16T7ZBBXG VSS9 VSS56 89HPES16T7ZBBXG VSS10 VSS57 VDDAPE1 VDDPE1 VDDCORE1...
  • Page 47 CR-16 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE16 3_3V 3_3V DS31 R221 89HPES16T7ZBBXG DS36 R226 M_REFCLK1P PEREFCLKP1 M_REFCLK1N DS32 R222 PEREFCLKN1 M_REFCLK2P PEREFCLKP2 DS27 R206 M_REFCLK2N PEREFCLKN2 89HPES16T7ZBBXG M_REFCLKM REFCLKM M_MSMBADDR3 MSMBADDR_4 M_CCLKUS M_MSMBADDR2 CCLKUS MSMBADDR_3 M_CCLKDS CCLKDS M_MSMBADDR1 MSMBADDR_2 1 of 7 M_MSMBADDR0 MSMBADDR_1 M_PERSTN M_B_PERST* TP18...
  • Page 48 CR-17 : @MEB16T7_LIB.MEB16T7(SCH_1):PAGE17 3_3VAUX 3_3VAUX 3_3VAUX 3_3VAUX 3_3VAUX 3_3VAUX 3_3V D_WAKE* B_WAKE* F_WAKE* 3_3V SN74LVC1G125 SN74LVC1G125 SN74LVC1G125 PCA9555 3_3VAUX 3_3VAUX INT# M_SCL 3_3VAUX 3_3VAUX M_SDA PA_ACTIVEN PA_LINKUPN I/O0.0 I/O1.0 I/O0.1 I/O1.1 PF_LINKUPN PF_ACTIVEN I/O0.2 I/O1.2 PE_LINKUPN PE_ACTIVEN I/O0.3 I/O1.3 PD_LINKUPN PD_ACTIVEN I/O0.4 I/O1.4...
  • Page 49 PCB Design Group STG ECN# : PCBECN-0025 Engineering Change Notice STGC-0082R01 STG DCN# : 18-610-000 Release/Effective Date: Project 11/14/2006 Current Fab Rev. Name 89EBPES16T7 - McKinley Eval Bd New Fab Rev. Documentation Affected: Originator's Approval: Assembly Drawing Bill Of Materials Drill File Fab Drawing Gerber Data...
  • Page 50 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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