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IDT
89EBPES12T3G2
Evaluation Board Manual
(Eval Board: 18-635-001)
October 2007
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2007 Integrated Device Technology, Inc.

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Summary of Contents for Renesas IDT 89EBPES12T3G2

  • Page 1 ® 89EBPES12T3G2 ™ Evaluation Board Manual (Eval Board: 18-635-001) October 2007 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2007 Integrated Device Technology, Inc.
  • Page 2 DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
  • Page 3: Table Of Contents

    Table of Contents ® Description of the EB12T3G2 Eval Board Notes Introduction .............................1-1 Board Features ..........................1-2 Hardware ..........................1-2 Software..........................1-2 Other............................1-2 Revision History ..........................1-2 Installation of the EB12T3G2 Eval Board EB12T3G2 Installation ........................2-1 Hardware Description ........................2-1 Reference Clocks..........................
  • Page 4 IDT Table of Contents Notes EB12T3G2 Eval Board Manual October 3, 2007...
  • Page 5 List of Tables ® Table 2.1 Clock Source Selection .......................2-1 Notes Table 2.2 Clock Frequency Selection ....................2-2 Table 2.3 Clock Spread Spectrum Selection ..................2-2 Table 2.4 SMA Connectors - Onboard Reference Clock ..............2-2 Table 2.5 External Power Connector - J1 ................... 2-3 Table 2.6 Downstream Reset Selection .....................
  • Page 6 IDT List of Tables Notes EB12T3G2 Eval Board Manual October 3, 2007...
  • Page 7 List of Figures ® Figure 1.1 Function Block Diagram of the EB12T3G2 Eval Board ............1-1 Notes EB12T3G2 Eval Board Manual October 3, 2007...
  • Page 8 IDT List of Figures Notes EB12T3G2 Eval Board Manual October 3, 2007...
  • Page 9: Introduction

    Chapter 1 Description of the EB12T3G2 Eval Board ® Introduction Notes The 89HPES12T3G2 switch (also referred to as PES12T3G2 in this manual) is a member of IDT’s PCI Express® standard (PCIe®) based line of products. It is a Gen2 3-port switch, with 4 serial lanes per port. One upstream port is provided for connecting to the root complex (RC), and up to two downstream ports are available for connecting to PCIe endpoints or to another switch.
  • Page 10: Board Features

    IDT Description of the EB12T3G2 Eval Board Board Features Notes Hardware PES12T3G2 PCIe 3 port switch – Three x4 ports, 12 PCIe lanes – PCIe Base Specification Revision 2.0 compliant – 12 GBps (96 Gbps) aggregate switching capacity – Up to 2048 byte maximum Payload Size –...
  • Page 11: Installation Of The Eb12T3G2 Eval Board

    Chapter 2 Installation of the EB12T3G2 Eval Board ® EB12T3G2 Installation Notes This chapter discusses the steps required to configure and install the EB12T3G2 evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1.
  • Page 12: Power Sources

    IDT Installation of the EB12T3G2 Eval Board Notes Clock Frequency Switch - S2[2:1] S2[2] S2[1] Clock Frequency Reserved 125 MHz 100 MHz (Default) <Reserved> Table 2.2 Clock Frequency Selection Clock Spread Spectrum Switch - S2[4:3] S2[4] S2[3] Spread% No Spread (Default) Down -0.75 Down -0.50 Center ±0.25...
  • Page 13: Pci Express Analog High Power Voltage Converter

    IDT Installation of the EB12T3G2 Eval Board Notes Signal +12V Table 2.5 External Power Connector - J1 PCI Express Analog High Power Voltage Converter A DC-DC converter (U18) provides a 2.5V PCI Express analog high power voltage (shown as VDDHA) to the PES12T3G2.
  • Page 14: Fundamental Reset

    IDT Installation of the EB12T3G2 Eval Board Fundamental Reset Notes There are two types of Fundamental Resets which may occur on the EB12T3G2 evaluation board: – Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI Express Reset (PERSTN) input pin of the PES12T3G2.
  • Page 15: Table 2.8 Boot Configuration Vector Switches S7 & S8 (On=0, Off=1)

    IDT Installation of the EB12T3G2 Eval Board Notes Signal Description RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12T3G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.
  • Page 16: Smbus Interfaces

    IDT Installation of the EB12T3G2 Eval Board SMBus Interfaces Notes The System Management Bus (SMBus) is a two-wire interface through which various system compo- nent chips can communicate. It is based on the principles of operation of I C. Implementation of the SMBus signals in the PCI Express connector is optional and may not be present on the host system.
  • Page 17: Smbus Master Interface

    IDT Installation of the EB12T3G2 Eval Board SMBus Master Interface Notes Connected to the master SMBus interface are three 16-bit I/O Expanders (PCA9555) and a serial EEPROM (24LC512). Three I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B).
  • Page 18: Miscellaneous Jumpers, Headers

    IDT Installation of the EB12T3G2 Eval Board Notes Miscellaneous Jumpers, Headers Miscellaneous Jumpers, Headers Ref. Type Default Description Designator W1-W3 Header 1-2 Shunted 1-2: 12.0V source from Upstream Port (Default) 2-3: 12.0V source from external power connector Header Shunted Disable EEPROM Write protect feature (Default) S6[1] Switch ON: Port2, Force hot-plug controller on...
  • Page 19: Pci Express Connectors

    IDT Installation of the EB12T3G2 Eval Board Notes Location Color Definition DS17 Green Port2: Linkup Indicator Green Port4: Linkup Indicator DS23 Green Port0: Linkup Indicator DS24 Green Port0: Activity Indicator Port2/4: Power Fault Indicator DS25 Green GPIO3 DS26 Green GPIO5 DS27 Green GPIO6...
  • Page 20 IDT Installation of the EB12T3G2 Eval Board Notes Side A Side B Ground PERn1 pair, Lane 1 PETp2 Transmitter differential Ground PETn2 pair, Lane 2 Ground Ground PERp2 Receiver differential Ground PERn2 pair, Lane 2 PETp3 Transmitter differential Ground PETn3 pair, Lane 3 Ground Ground...
  • Page 21 IDT Installation of the EB12T3G2 Eval Board Notes Side A Side B PETn10 pair, Lane 10 Ground Ground PERp10 Receiver differential Ground PERn10 pair, Lane 10 PETp11 Transmitter differential Ground PETn11 pair, Lane 11 Ground Ground PERp11 Receiver differential Ground PERn11 pair, Lane 11 PETp12...
  • Page 22: Eb12T3G2 Board Figure

    IDT Installation of the EB12T3G2 Eval Board EB12T3G2 Board Figure EB12T3G2 Eval Board Manual 2 - 12 October 3, 2007...
  • Page 23 IDT Installation of the EB12T3G2 Eval Board EB12T3G2 Eval Board Manual 2 - 13 October 3, 2007...
  • Page 24 IDT Installation of the EB12T3G2 Eval Board Notes EB12T3G2 Eval Board Manual 2 - 14 October 3, 2007...
  • Page 25: Software For The Eb12T3G2 Eval Board

    Chapter 3 Software for the EB12T3G2 Eval Board ® Introduction Notes This chapter discusses some of the main features of the available software to give users a better under- standing of what can be achieved with the EB12T3G2 evaluation board using the device management soft- ware.
  • Page 26 IDT Software for the EB12T3G2 Eval Board Notes EB12T3G2 Eval Board Manual 3 - 2 October 3, 2007...
  • Page 27: Schematics

    Chapter 4 Schematics ® Schematics Notes EB12T3G2 Eval Board Manual 4 - 1 October 3, 2007...
  • Page 28 REVISIONS DESCRIPTION DATE CHANGE BY STGC-0139R01 INITIAL RELEASE 2007-10-02 K. LEUNG SHEET DESCRIPTION ------------------------------- TITLE PAGE RESET, POWER CONNECTOR POWER REGULATORS CLOCKS I/O EXP, WAKE, ATTN HOT PLUG CONTROLLERS HOT PLUG - MOSFETS PORT 0 EDGE CONN (U/S) PORT 2 CONNECTOR (D/S) PORT 4 CONNECTOR (D/S) PES12T3G2 - EEPROM, JTAG PES12T3G2 - POWER...
  • Page 29 3_3V 3_3V 3_3V 3_3V 3_3V 3_3V POWER INDICATOR BOARD RESET PLACE NEAR TOP EDGE LABEL 'POWER' PERST_N 3_3V M_PERSTN PERST_N TLC7733D RESINN SENSE RESET CONTROL RESETN SN74LVC1G125 LABEL 'GND' PB_SW STIFF_6P 12V_DS 12_0V +12.0V -> +3.3V 3_3V 3_3VIO POWER CONN +12V VO_SEN+ Track...
  • Page 30 3_3V 3_3V VDDCORE, 1.0V VDDPETA, 1.0V +1.0V_CORE +1.0V_VDDTA 120OHM 120OHM EN5330 VOUT1 EN5330 VOUT1 400MA 400MA VOUT2 VOUT2 120OHM 120OHM FB10 VOUT3 VOUT3 400MA 400MA VOUT4 VOUT4 120OHM 120OHM FB11 VOUT5 VOUT5 400MA 400MA AVIN VOUT6 AVIN VOUT6 VOUT_PAD VOUT_PAD ENABLE VSENSE ENABLE...
  • Page 31 3_3V 3_3V 120OHM 3_3V 3_3V PLACE NEAR U5 P0_REFCLKP ICS9DB803 SM0805 P0_REFCLKN VDDA SRC_IN DIF_0 P4_REFCLKP SRC_IN# DIF_0# P4_REFCLKN SM0805 M_REFCLK1P 10 5 6 P4_PWRGDN OE0# DIF_1 DIF_1# M_REFCLK1N OE1# SM_SW8 DIF_2 PLACE NEAR U4 SSC_S0 OE2# DIF_2# ICS557-03 SSC_S1 SSC_SS0 OE3# DIF_3...
  • Page 32 3_3V 3_3V 3_3VAUX 3_3VAUX P4_WAKE_N PCA9555 M_IOINTN0 INT# M_SCL 11 5 M_SDA 5 11 P0_WAKE_N P2_APN P4_APN I/O0.0 I/O1.0 P2_PDN P4_PDN I/O0.1 I/O1.1 P2_PFN P4_PFN SN74LVC1G125 I/O0.2 I/O1.2 P2_MRLN P4_MRLN I/O0.3 I/O1.3 P2_AIN P4_AIN TP10 I/O0.4 I/O1.4 P2_PIN P4_PIN I/O0.5 I/O1.5 P2_PEP P4_PEP...
  • Page 33 12V_DS 3_3V 3_3V 3_3V 3_3V MIC2591B P2_VAUX VSTBYA VAUXA VSTBYB 12VINA IREF P2_12VSENSE 12VSENSEA RFILTER P2_12VGATE 12VGATEA CFILTERA P2_12VOUT CFILTERB 12VOUTA P2_F_ON FORCE_ONA_N P4_F_ON FORCE_ONB_N 3VINA GPI_A0 P2_3VSENSE GPI_B0 3VSENSEA P2_3VGATE 3VGATEA P2_PEP AUXENA P4_PEP P2_3VOUT AUXENB 3VOUTA P2_PWRGDN PWRGDA_N P4_PWRGDN PWRGDB_N P2_PFN...
  • Page 34 P2_PCIE_3_3AUX 3_3VAUX 3_3VAUX P4_PCIE_3_3AUX P4_VAUX P2_VAUX 12V_DS P4_12V 12V_DS P2_12V 0.02 0.02 P4_12VSENSE P2_12VSENSE P4_12VGATE P2_12VGATE P4_12VOUT P2_12VOUT 0.022UF 0.022UF R119 R127 PMOSFET PMOSFET 6800PF 6800PF P4_3_3V P2_3_3V 3_3V 3_3V 0.012 0.012 P4_3VSENSE P2_3VSENSE P4_3VGATE P2_3VGATE P4_3VOUT NMOSFET P2_3VOUT NMOSFET R118 R126 89EBPES12T3G2...
  • Page 35 P0_3_3V 3_3VAUX 12_0V 12_0V LABEL PINS: 3_3V 1 NC 2 SMBCLK R158 3 GND R159 4 SMBDATA PCIE_X4_EDGE +12V PRSTN1# +12V +12V RSVD +12V R160 M_SSMBCLK SMCLK JTAG_TCK R161 M_SSMBDATA SMDAT JTAG_TDI JTAG_TDO +3.3V JTAG_TMS JTAG_TRSTN +3.3V 3.3VAUX +3.3V P0_WAKE_N PERST_N WAKE# PERST#...
  • Page 36 P2_PCIE_3_3AUX P2_3_3V P2_12V P2_12V P2_3_3V DS22 PCI_X16_CONN R151 +12V PRSTN1# +12V +12V RSVD +12V M_SSMBCLK R149 SMCLK JTAG2 M_SSMBDATA R150 SMDAT JTAG3 JTAG4 +3.3V JTAG5 JTAG1 +3.3V 3.3VAUX +3.3V P2_WAKE_N P2_PERST_N WAKE# PERST# RSVD P2_REFCLKP REFCLK+ P2_PETP0 P2_REFCLKN PETP0 REFCLK- P2_PETN0 PETN0 P2_PERP0...
  • Page 37 P4_PCIE_3_3AUX P4_3_3V P4_12V P4_12V P4_3_3V DS10 PCI_X16_CONN R131 +12V PRSTN1# +12V +12V RSVD +12V M_SSMBCLK R129 SMCLK JTAG2 M_SSMBDATA R130 SMDAT JTAG3 JTAG4 +3.3V JTAG5 JTAG1 +3.3V 3.3VAUX +3.3V P4_WAKE_N P4_PERST_N WAKE# PERST# RSVD P4_REFCLKP REFCLK+ P4_PETP0 P4_REFCLKN PETP0 REFCLK- P4_PETN0 PETN0 P4_PERP0...
  • Page 38 SILKSCREEN 3_3V LABEL LEDS: DS25 R178 GPIO3 3_3V 89HPES12T3G2 (1 of 5) DS26 R179 GPIO5 M_REFCLK1N PE0REFCLKN DS27 R180 GPIO6 M_REFCLK1P PE0REFCLKP DS28 R181 GPIO11 M_REFCLKM REFCLKM M_CCLKUS CCLKUS M_CCLKDS CCLKDS M_PERSTN PERSTN M_RSTHALT RSTHALT P0_REFRES 89HPES12T3G2 (2 of 5) M_SWMODE2 SWMODE2 P2_REFRES...
  • Page 39 +2.5V_VDDHA 3_3VIO +1.0V_VDDTA +1.0V_VDDA +1.0V_CORE VSS33 VSS128 VSS34 VSS127 VSS35 VSS126 VSS36 VSS125 VSS37 VSS124 VSS38 VSS123 VSS39 VSS122 VSS40 VSS121 VSS41 VDDCORE27 VSS120 VSS42 VDDPETA14 VDDCORE28 VSS119 VSS43 VDDPETA13 VDDCORE29 VSS118 VSS44 VDDPETA12 VDDCORE30 VSS117 VSS45 VDDPETA11 VDDCORE31 VSS116 VSS46 VDDPETA10 VDDCORE32...
  • Page 40 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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