FIC PA-2013 Manual page 44

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The options are: Enabled (Default), Disabled.
Sustained 3T Write
When enabled, allows the CPU to compele the memory writes in 3 clocks.
The options are: Enabled (Default), Disabled.
Cache Pipeline
When enabled, it makes the read/write speed between the CPU and the
cache RAMs faster. The options are: Enabled (Default), Disabled.
DRAM Read Pipeline
When enabled, it makes the data read speed from memory modules to cache
RAMs faster. The options are: Enabled (Default), Disabled.
Read Around Write
This feature speeds up data read performance when it stays Enabled.
The options are: Enabled (Default), Disabled.
Memory ECC Check
Set at Enabled, if the RAM modules support ECC function.
The options are: Enabled, Disabled (Default).
Linear Burst
If a Cyrix or an IBM CPU installed, this feature appears and it allows you to
configure the CPU to SRAM data read/write mode. If you use a Cyrix CPU,
select Enabled; if you use an Intel CPU or AMD-K6 CPU, please stay with
the default value, Disabled. Please refer to SRAM, Page 11, Chapter 2.
Bank 0/1 DRAM Timing;
Bank 2/3 DRAM Timing;
Bank 4/5 DRAM Timing
This feature allows you to select the DRAM read/write speed.
The options are: Fast (Default), Normal, Turbo.
SDRAM Cycle Length
This feature appears only when SDRAM DIMM/s is installed (BIOS auto
detection). If the CAS latency of your SDRAM DIMM is 2, set at 2 to
enhance the system performance. If the CAS latency of your SDRAM
DIMM is 3, stay with the default setting, 3.
The options are: 2, 3 (Default).
BIOS Setup
33

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