Supermicro X12SDV-4C-SPT4F User Manual page 64

Super X12SDV-4C/8C/10C-SPT4F User's Manual
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Processor Frequency
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Processor Max Ratio
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Processor Min Ratio
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Microcode Revision
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L1 Cache RAM (Per Core)
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L2 Cache RAM (Per Core)
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L3 Cache RAM (Per Package)
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Processor 0 Version
CPU1 Core Disable Bitmap
CPU1 Core Disable Bitmap
Available Bitmap
CPU Core Count
CPU1 Cores Enable
Select 0 to enable all cores or FFFFFFFFFFF to disable all cores. One core must be
enabled.
Hyper-Threading (ALL)
Select Enable to support Intel Hyper-threading Technology to enhance CPU performance.
The options are Disable and Enable.
Hardware Prefetcher
If set to Enable, the hardware prefetcher prefetches streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Enable
and Disable.
Adjacent Cache Prefetch
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Enable and Disable.
DCU Streamer Prefetcher (Available when supported by the CPU)
Select Enable to enable the Data Cache Unit (DCU) Streamer Prefetcher, which streams
and prefetches data and sends it to the Level 1 data cache to improve data processing and
system performance. The options are Enable and Disable.
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