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Alpha Data ADM-PA120 User Manual

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ADM-PA120
User Manual
Document Revision: 1.2
18th July 2023

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Summary of Contents for Alpha Data ADM-PA120

  • Page 1 ADM-PA120 User Manual Document Revision: 1.2 18th July 2023...
  • Page 2 ADM-PA120 User Manual © 2023 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    ADM-PA120 User Manual Table Of Contents Introduction ............................1 Order Code ............................ 1 Key Features ..........................2 Board Information ..........................3 Physical Specifications ........................3 PCIe Handle Installation ........................ 4 Chassis Requirements ........................5 2.3.1 Handling Instructions ......................... 5 2.3.2 PCI Express ..........................
  • Page 4 List of Figures Figure 1 ADM-PA120 Fully Assembled ......................1 Figure 2 ADM-PA120 Product Photo ....................... 2 Figure 3 ADM-PA120 PCIe Handle Installation ....................4 Figure 4 Retention Points ..........................5 Figure 5 Thermal Performance ........................7 Figure 6 ADM-PA120 Block Diagram ....................... 8 Figure 7 Switches .............................

  • Page 5: Introduction

    ADM-PA120 User Manual 1 Introduction The ADM-PA120 is a high-performance reconfigurable computing card featuring the latest AMD Adaptive Compute Acceleration Platform (ACAP) platform known as Versal. The PCIe form factor is ideal for Data Center applications and general evaluation and deployment of this architecture. The card features three QSFP-DD interfaces, four banks of 64-bit LPDDR4-SDRAM, front panel Ethernet, 1pps input, 10MHz input, trigger I/O, RJ45 G.703 ToD/1PPS, PMOD, and USB.

  • Page 6: Key Features

    Front panel and rear edge JTAG access via USB port • ACAP configurable over USB/JTAG and SPI configuration flash • Voltage, current, and temperature monitoring • Digilent PMOD 3.3V, 12-pin interface accessible to PL • 6 user LEDs Figure 2 : ADM-PA120 Product Photo Page 2 Introduction ad-ug-1492_v1_2.pdf...

  • Page 7: Board Information

    ADM-PA120 User Manual 2 Board Information 2.1 Physical Specifications The ADM-PA120 complies with PCI Express CEM revision 5.0. Description Measure PCB Dy 111.15 mm PCB Dx 254 mm Total Dz 19.9 mm Table 1 : Mechanical Dimensions (PCB only) Description...

  • Page 8: Pcie Handle Installation

    ADM-PA120 User Manual 2.2 PCIe Handle Installation The ADM-PA120 ships fully assembled. There is a PCIe compliant handle shipped in a separate bag within the product package. This handle assembly includes a plastic handle and a metal bracket. The bracket simulates the full length PCIe card length, and frequently lines up with server retention clips.

  • Page 9: Chassis Requirements

    2.3.2 PCI Express The ADM-PA120 is capable of PCIe Gen 1/2/3/4 with 1/4/8/16 lanes, and PCIe Gen 5 with 1/4/8 lanes when using the AMD Integrated Block for PCI Express. PCIe Gen 5x8 can be bifurcated into two slots to achieve an aggregate bandwidth of a 16 lane connection.

  • Page 10: Power Requirements

    2.3.4 Power Requirements The ADM-PA120 draws power from the PCIe Edge and the 8-pin ATX power connector. The ADM-PA120 does not use or require the 3.3V power from the PCIe Edge (though it does use 3.3V AUX). To operate with PCIe edge only, ensure SW2-6 is OFF (see Switches).

  • Page 11: Thermal Performance

    The ADM-PA120 comes with a heat sink to avoid thermal overstress of ACAP, since it is typically the hottest point on the card. The ACAP die temperature must remain under 100 degrees Celsius. To estimate the ACAP die temperature: first take your total board power (see next paragraph), then multiply by Theta JA from the graph below, and add the resulting temperature to your system internal ambient temperature.

  • Page 12: Functional Description

    3 Functional Description 3.1 Overview The ADM-PA120 is a high-performance reconfigurable computing card featuring the latest AMD Adaptive Compute Acceleration Platform (ACAP) platform with the Versal XCVP1202 or XCVP1502, three QSFP-DD interfaces, PCIe Gen4x16 or 2xGen5x8, four banks of LPDDR4 each 64 bits wide, GEM0 Ethernet, QSPI, uSD, USB, UART, a Digilent PMOD site, flexible front panel I/O (RS485 for ToD, 1PPS, 10MHz, and general purpose I/ O), and a robust system monitor.

  • Page 13: Switches

    ADM-PA120 User Manual 3.1.1 Switches The ADM-PA120 has two octal DIP switch SW1 and SW2, located on the rear side of the board. The function of each switch is detailed below: Figure 7 : Switches Factory Switch Function OFF State...

  • Page 14: Leds

    ADM-PA120 User Manual 3.1.2 LEDs There are 10 LEDs on the ADM-PA120, 6 of which are general purpose and whose meaning can be defined by the user. The other 4 have fixed functions described below: User LEDs Status LEDs USER_LED_G5...

  • Page 15: Clocking

    10Mhz and 1PPS inputs. The Si5402 can be reconfigured over I2C using with a controller embedded in the FPGA design. Using this chip requires support directly from Skyworks. Alpha Data does not support application software for this device.

  • Page 16: Figure 9 Clock Topology

    ADM-PA120 User Manual Versal ACAP 33.333MHz Fixed Source PS_REF_CLK (CIPS REF_CLK_503) LMK61E2 Programmable Buffer Source 50ppm MGTREFCLK0 SI5344 (SI5344_OUT0) CLKIN0 OUT0 (1DSPLL) MGTREFCLK1 CLKIN1 OUT1 (SI5402_OUT7) CLKIN2 OUT2 I2C + CLKIN3 XA/XB OUT3 MGTREFCLK0 CNTRL (MGT_PROGCLK_0) MGTREFCLK1 (SI5402_OUT6) MGTREFCLK0 (SI5344_OUT1)

  • Page 17: Lmk61E2

     The ADM-PA120 uses two LMK61E2 devices in the clock architecture. These can be accessed through either the USB or PCIe link using the AVR2UTIL application. See additional details on avr2util in the section: Micro USB Interface.

  • Page 18: Si5344

    ADM-PA120 User Manual 3.2.2 Si5344 If jitter attenuation is required please see the reference documentation for the Si5344. https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/si5345-44-42-d-datasheet.pdf  There is one input clock that originates in the ACAP PL (board net name SI5344_IN0_P/N). This allows the application design to feed this clock from anywhere within the ACAP PL.

  • Page 19: Pcie Reference Clocks

    Complete Pinout Table for pin locations. In the Alpha Data provided board file, this is called "refclk_100m" 3.2.6 PS Reference Clock (PS_REF_CLK) A 33.333MHz clock is fed into the dedicated REF_CLK_503 pin to drive the processor system. This clock has an accuracy tolerance of 50ppm.

  • Page 20: Pci Express

    ADM-PA120 User Manual 3.3 PCI Express The ADM-PA120 is capable of PCIe Gen 1/2/3/4 with 1/4/8/16 lanes and bifurcated Gen 5 with 1/4/8 lanes. The ACAP drives these lanes directly using the Integrated PCI Express block from AMD. Negotiation of PCIe link speed and number of lanes is generally automatic and does not require user intervention.

  • Page 21: Qsfp-Dd

    ADM-PA120 User Manual 3.5 QSFP-DD Three QSFP-DD cages are available at the front panel. These cages are capable of housing either QSFP28 or QSFP-DD cables (backwards compatible). Both active optical and passive copper QSFP-DD/QSFP28 compatible models are fully compliant. The communication interface can run at up to 28Gbps per channel on GTY and 56 Gbps per channel on GTM.

  • Page 22: Front I/O Timing Inputs

    ADM-PA120 User Manual 3.6 Front I/O timing inputs The ADM-PA120 includes a number of timing and signal inputs that are critical for high performance synchronous networking. This section details the four available timing inputs. Figure 13 : Front I/O timing inputs 3.6.1 Trigger Input/Output (I/O)

  • Page 23: 1Pps Input

    ADM-PA120 User Manual 3.6.2 1PPS Input One of the SMA connectors is used for a 1PPS input. This is a general input that can be used for any signal that complies with ITU-T G.703 section 19.2, voltage specifications for an unbalanced 50 ohm input signal.

  • Page 24: Time Of Day (Tod) / One Pulse Per Second (1Pps)

    ADM-PA120 User Manual 3.6.4 G.703 Time of Day (ToD) / One Pulse per Second (1PPS) One of the RJ45 jacks at the front panel is dedicated to comply with G.703 ToD/1PPS signals. These connections comply with ITU-T G.703 section 19.1. The electrical standard is met with RS485 transceivers. These transceivers can also be used for generic RS485 communication networks.

  • Page 25: System Monitor

    ADM-PA120 User Manual 3.7 System Monitor The ADM-PA120 has the ability to monitor select temperatures, voltages, and currents in order to provide an indication of board health. The monitoring is implemented using an AVR microcontroller. This information can be read out via USB using the avr2util utility. Alternatively, the sensor information can be read directly by the ACAP or via PCIe if RD-PA120 is purchased (reference design package).

  • Page 26: System Monitor Status Leds

    ADM-PA120 User Manual 3.7.1 System Monitor Status LEDs LEDs D20 (Red) and D21 (Green) indicate the card health status. LEDs Status Green Running and no alarms Green + Red Standby (Powered off) Flashing Green + Flashing Red Attention - critical alarm active...

  • Page 27: Micro Usb Interface

    The ADM-PA120 utilizes the Digilent USB-JTAG converter which is supported by the AMD software tool suite. Simply connect a micro-USB AB type cable between the ADM-PA120 USB port and a host computer with Vivado installed. Vivado Hardware Manager will automatically recognize the ACAP and allow you to configure the ACAP and the SPI configuration Flash memory.

  • Page 28: Configuration

    SPI device (2x Micron part number MT25QU01GCBB8E12). The ADM-PA120 is shipped with a simple "hello world" application that prints text on UART0 loaded into QSPI. On request, Alpha Data can pre-load custom bitstreams during production test. Please contact sales@alpha-data.com in order to discuss this possibility.

  • Page 29: Configuration Via Jtag

    ADM-PA120 User Manual 3.9.3 Configuration via JTAG A micro-USB AB Cable may be attached to the front panel or rear edge USB port. This permits the ACAP to be reconfigured using the AMD Vivado Hardware Manager and Vitis via the integrated Digilent JTAG converter box.

  • Page 30: Ulpi Usb Interface

    USB cable. This UART interface will appear in the host system as soon as the USB cable is installed, even before the ADM-PA120 is powered up. This interface is suitable to capture power-on messages from the processor.

  • Page 31: Gem0

    ADM-PA120 User Manual 3.12 GEM0 The Gigabit Ethernet Manager (GEM0) is interfaced with a Microchip VSC8541 to provide 10/100/1000 Base-T Ethernet to the ACAP. This interface is accessible at the front panel. A dedicated reset signal is connected to the MIO pins, see signal name GEM0_RST_L in Complete Pinout Table.

  • Page 32: Pmod

    ADM-PA120 User Manual 3.14 PMOD The ADM-PA120 includes a twelve-pin right angle connector PMOD host interface at the rear edge of the card with a full 0.9" clearance. This interface is connected to the PL of the ACAP. See the PMOD Specification for full details.

  • Page 33: Appendix A Mio Map

    ADM-PA120 User Manual Appendix A: MIO Map Pin Number Pin Name Signal Name Comment PMC_MIO0_500 QSPI0_CLK Dual-Parallel Quad SPI PMC_MIO1_500 QSPI0_IO[1] Dual-Parallel Quad SPI PMC_MIO2_500 QSPI0_IO[2] Dual-Parallel Quad SPI PMC_MIO3_500 QSPI0_IO[3] Dual-Parallel Quad SPI PMC_MIO4_500 QSPI0_IO[0] Dual-Parallel Quad SPI PMC_MIO5_500...
  • Page 34 ADM-PA120 User Manual Pin Number Pin Name Signal Name Comment PMC_MIO34_501 SD1_SEL SD1_3.0 PMC_MIO35_501 PMC_MIO36_501 PMC_MIO37_501 GEM0_RST_L GEM0 Ethernet PMC_MIO38_501 PCIE_PERST_B PCIE PMC_MIO39_501 PCIE_PERST_B PCIE PMC_MIO40_501 PMC_MIO41_501 PMC_MIO42_501 UART0_RXD Not availabe until full power PMC_MIO43_501 UART0_TXD Not availabe until full power...

  • Page 35: Table 11 Mio Map

    ADM-PA120 User Manual Pin Number Pin Name Signal Name Comment LPD_MIO18_502 LPD_MIO19_502 LPD_MIO20_502 LPD_MIO21_502 LPD_MIO22_502 LPD_MIO23_502 LPD_MIO24_502 GEM0_MDIO_CLK GEM0 Ethernet LPD_MIO25_502 GEM0_MDIO_DATA GEM0 Ethernet Table 11 : MIO Map MIO Map Page 31 ad-ug-1492_v1_2.pdf...

  • Page 36: Appendix B Complete Pinout Table

    ADM-PA120 User Manual Appendix B: Complete Pinout Table Signal Name Pin Name IO Voltage Bank Number 10MHZ_PIN_N IO_L12N_GC_XCC_N4P1_712 10MHZ_PIN_P IO_L12P_GC_XCC_N4P0_712 1PPS_FPGA IO_L25P_N8P2_712 485_0_DATA_FPGA IO_L26P_N8P4_712 485_0_DE/RE_L_FPGA IO_L10P_N3P2_712 485_1_DATA_FPGA IO_L26N_N8P5_712 485_1_DE/RE_L_FPGA IO_L11P_N3P4_712 AVR_B2U_1V5 IO_L0P_XCC_N0P0_712 AVR_MON_CLK_1V5 IO_L1P_N0P2_712 AVR_U2B_1V5 IO_L0N_XCC_N0P1_712 BF24 DO_NOT_USE IO_L26N_N8P5_M1P107_704 BF23...
  • Page 37 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number GEM0_RXD_0 LPD_MIO7_502 GEM0_RXD_1 LPD_MIO8_502 GEM0_RXD_2 LPD_MIO9_502 GEM0_RXD_3 LPD_MIO10_502 GEM0_TX_CLK LPD_MIO0_502 GEM0_TX_CTRL LPD_MIO5_502 GEM0_TXD_0 LPD_MIO1_502 GEM0_TXD_1 LPD_MIO2_502 GEM0_TXD_2 LPD_MIO3_502 GEM0_TXD_3 LPD_MIO4_502 AM13 LPDDR4_0_CH0_CA_A[0] IO_L22N_N7P3_M0P45_700 AL14 LPDDR4_0_CH0_CA_A[1] IO_L22P_N7P2_M0P44_700 AK13 LPDDR4_0_CH0_CA_A[2] IO_L21P_XCC_N7P0_M0P42_700...
  • Page 38 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number LPDDR4_0_CH0_DMI_B[0] IO_L9P_GC_XCC_N3P0_M0P18_700 LPDDR4_0_CH0_DMI_B[1] IO_L15P_XCC_N5P0_M0P84_701 BD11 LPDDR4_0_CH0_DQ_A[0] IO_L2N_N0P5_M0P5_700 BC12 LPDDR4_0_CH0_DQ_A[1] IO_L2P_N0P4_M0P4_700 LPDDR4_0_CH0_DQ_A[10] IO_L5N_N1P5_M0P65_701 LPDDR4_0_CH0_DQ_A[11] IO_L4P_N1P2_M0P62_701 LPDDR4_0_CH0_DQ_A[12] IO_L2N_N0P5_M0P59_701 LPDDR4_0_CH0_DQ_A[13] IO_L2P_N0P4_M0P58_701 LPDDR4_0_CH0_DQ_A[14] IO_L1N_N0P3_M0P57_701 LPDDR4_0_CH0_DQ_A[15] IO_L1P_N0P2_M0P56_701 BB10 LPDDR4_0_CH0_DQ_A[2] IO_L1N_N0P3_M0P3_700 BA10 LPDDR4_0_CH0_DQ_A[3] IO_L1P_N0P2_M0P2_700 BF10...
  • Page 39 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AY14 LPDDR4_0_CH0_DQS_C_B[0] IO_L6N_GC_XCC_N2P1_M0P13_700 BF12 LPDDR4_0_CH0_DQS_C_B[1] IO_L12N_GC_XCC_N4P1_M0P79_701 LPDDR4_0_CH0_DQS_T_A[0] IO_L3P_XCC_N1P0_M0P6_700 LPDDR4_0_CH0_DQS_T_A[1] IO_L0P_XCC_N0P0_M0P54_701 AW14 LPDDR4_0_CH0_DQS_T_B[0] IO_L6P_GC_XCC_N2P0_M0P12_700 BE13 LPDDR4_0_CH0_DQS_T_B[1] IO_L12P_GC_XCC_N4P0_M0P78_701 AT10 LPDDR4_0_CH0_RESET_N[0] IO_L25P_N8P2_M0P50_700 BN16 LPDDR4_0_CH1_CA_A[0] IO_L4N_N1P3_M0P117_702 BM17 LPDDR4_0_CH1_CA_A[1] IO_L4P_N1P2_M0P116_702 BN15 LPDDR4_0_CH1_CA_A[2] IO_L5N_N1P5_M0P119_702 BM16...
  • Page 40 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BL14 LPDDR4_0_CH1_DQ_A[1] IO_L11N_N3P5_M0P131_702 BJ12 LPDDR4_0_CH1_DQ_A[10] IO_L19P_N6P2_M0P92_701 BN12 LPDDR4_0_CH1_DQ_A[11] IO_L20N_N6P5_M0P95_701 BK10 LPDDR4_0_CH1_DQ_A[12] IO_L23N_N7P5_M0P101_701 BL10 LPDDR4_0_CH1_DQ_A[13] IO_L22N_N7P3_M0P99_701 BK11 LPDDR4_0_CH1_DQ_A[14] IO_L19N_N6P3_M0P93_701 BL11 LPDDR4_0_CH1_DQ_A[15] IO_L22P_N7P2_M0P98_701 BJ14 LPDDR4_0_CH1_DQ_A[2] IO_L7N_N2P3_M0P123_702 BH14 LPDDR4_0_CH1_DQ_A[3] IO_L7P_N2P2_M0P122_702 BL18 LPDDR4_0_CH1_DQ_A[4]...
  • Page 41 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BM11 LPDDR4_0_CH1_DQS_T_A[1] IO_L21P_XCC_N7P0_M0P96_701 AT17 LPDDR4_0_CH1_DQS_T_B[0] IO_L18P_XCC_N6P0_M0P144_702 LPDDR4_0_CH1_DQS_T_B[1] IO_L6P_GC_XCC_N2P0_M0P66_701 LPDDR4_0_CH1_RESET_N[0] IO_L25N_N8P3_M0P51_700 AW22 LPDDR4_1_CH0_CA_A[0] IO_L22N_N7P3_M1P45_703 AV22 LPDDR4_1_CH0_CA_A[1] IO_L22P_N7P2_M1P44_703 AV18 LPDDR4_1_CH0_CA_A[2] IO_L21P_XCC_N7P0_M1P42_703 AW20 LPDDR4_1_CH0_CA_A[3] IO_L23N_N7P5_M1P47_703 AT19 LPDDR4_1_CH0_CA_A[4] IO_L19P_N6P2_M1P38_703 AU18 LPDDR4_1_CH0_CA_A[5] IO_L19N_N6P3_M1P39_703 BB22...
  • Page 42 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BH22 LPDDR4_1_CH0_DQ_A[12] IO_L8N_N2P5_M1P17_703 BG21 LPDDR4_1_CH0_DQ_A[13] IO_L8P_N2P4_M1P16_703 BH21 LPDDR4_1_CH0_DQ_A[14] IO_L10P_N3P2_M1P20_703 BG20 LPDDR4_1_CH0_DQ_A[15] IO_L7P_N2P2_M1P14_703 BB23 LPDDR4_1_CH0_DQ_A[2] IO_L16N_N5P3_M1P87_704 BA24 LPDDR4_1_CH0_DQ_A[3] IO_L16P_N5P2_M1P86_704 AT25 LPDDR4_1_CH0_DQ_A[4] IO_L14P_N4P4_M1P82_704 AV24 LPDDR4_1_CH0_DQ_A[5] IO_L13N_N4P3_M1P81_704 AU24 LPDDR4_1_CH0_DQ_A[6] IO_L14N_N4P5_M1P83_704 AU23 LPDDR4_1_CH0_DQ_A[7]...
  • Page 43 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BE20 LPDDR4_1_CH0_RESET_N[0] IO_L25P_N8P2_M1P50_703 BN31 LPDDR4_1_CH1_CA_A[0] IO_L4N_N1P3_M1P117_705 BM31 LPDDR4_1_CH1_CA_A[1] IO_L4P_N1P2_M1P116_705 BN30 LPDDR4_1_CH1_CA_A[2] IO_L5N_N1P5_M1P119_705 BN29 LPDDR4_1_CH1_CA_A[3] IO_L5P_N1P4_M1P118_705 BL28 LPDDR4_1_CH1_CA_A[4] IO_L1P_N0P2_M1P110_705 BM28 LPDDR4_1_CH1_CA_A[5] IO_L1N_N0P3_M1P111_705 BB30 LPDDR4_1_CH1_CA_B[0] IO_L14P_N4P4_M1P136_705 BC30 LPDDR4_1_CH1_CA_B[1] IO_L14N_N4P5_M1P137_705 BE28 LPDDR4_1_CH1_CA_B[2]...
  • Page 44 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AV25 LPDDR4_1_CH1_DQ_A[15] IO_L19P_N6P2_M1P92_704 BH29 LPDDR4_1_CH1_DQ_A[2] IO_L10P_N3P2_M1P128_705 BJ30 LPDDR4_1_CH1_DQ_A[3] IO_L8N_N2P5_M1P125_705 BJ29 LPDDR4_1_CH1_DQ_A[4] IO_L10N_N3P3_M1P129_705 BK28 LPDDR4_1_CH1_DQ_A[5] IO_L11N_N3P5_M1P131_705 BG28 LPDDR4_1_CH1_DQ_A[6] IO_L7N_N2P3_M1P123_705 BF27 LPDDR4_1_CH1_DQ_A[7] IO_L7P_N2P2_M1P122_705 BD24 LPDDR4_1_CH1_DQ_A[8] IO_L23P_N7P4_M1P100_704 BE25 LPDDR4_1_CH1_DQ_A[9] IO_L23N_N7P5_M1P101_704 AT28 LPDDR4_1_CH1_DQ_B[0]...
  • Page 45 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AV31 LPDDR4_2_CH0_CA_A[2] IO_L21P_XCC_N7P0_M2P42_706 AW32 LPDDR4_2_CH0_CA_A[3] IO_L23N_N7P5_M2P47_706 AT31 LPDDR4_2_CH0_CA_A[4] IO_L19P_N6P2_M2P38_706 AU32 LPDDR4_2_CH0_CA_A[5] IO_L19N_N6P3_M2P39_706 BA33 LPDDR4_2_CH0_CA_B[0] IO_L16P_N5P2_M2P32_706 AY35 LPDDR4_2_CH0_CA_B[1] IO_L14N_N4P5_M2P29_706 BC34 LPDDR4_2_CH0_CA_B[2] IO_L17N_N5P5_M2P35_706 BB34 LPDDR4_2_CH0_CA_B[3] IO_L17P_N5P4_M2P34_706 BA31 LPDDR4_2_CH0_CA_B[4] IO_L13N_N4P3_M2P27_706 AY32 LPDDR4_2_CH0_CA_B[5]...
  • Page 46 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BE37 LPDDR4_2_CH0_DQ_A[4] IO_L17P_N5P4_M2P88_707 BA36 LPDDR4_2_CH0_DQ_A[5] IO_L13N_N4P3_M2P81_707 BB35 LPDDR4_2_CH0_DQ_A[6] IO_L13P_N4P2_M2P80_707 AY36 LPDDR4_2_CH0_DQ_A[7] IO_L14P_N4P4_M2P82_707 BG35 LPDDR4_2_CH0_DQ_A[8] IO_L8N_N2P5_M2P17_706 BF35 LPDDR4_2_CH0_DQ_A[9] IO_L8P_N2P4_M2P16_706 BE44 LPDDR4_2_CH0_DQ_B[0] IO_L5P_N1P4_M2P64_707 BD44 LPDDR4_2_CH0_DQ_B[1] IO_L4N_N1P3_M2P63_707 BM34 LPDDR4_2_CH0_DQ_B[10] IO_L4P_N1P2_M2P8_706 BN35 LPDDR4_2_CH0_DQ_B[11]...
  • Page 47 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AU39 LPDDR4_2_CH1_CA_A[5] IO_L1N_N0P3_M2P111_708 AH42 LPDDR4_2_CH1_CA_B[0] IO_L14P_N4P4_M2P136_708 AJ42 LPDDR4_2_CH1_CA_B[1] IO_L14N_N4P5_M2P137_708 AL41 LPDDR4_2_CH1_CA_B[2] IO_L17N_N5P5_M2P143_708 AJ40 LPDDR4_2_CH1_CA_B[3] IO_L13N_N4P3_M2P135_708 AH41 LPDDR4_2_CH1_CA_B[4] IO_L13P_N4P2_M2P134_708 AK41 LPDDR4_2_CH1_CA_B[5] IO_L17P_N5P4_M2P142_708 AU42 LPDDR4_2_CH1_CK_C_A[0] IO_L0N_XCC_N0P1_M2P109_708 AJ43 LPDDR4_2_CH1_CK_C_B[0] IO_L12N_GC_XCC_N4P1_M2P133_708 AT43 LPDDR4_2_CH1_CK_T_A[0]...
  • Page 48 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AU41 LPDDR4_2_CH1_DQ_A[7] IO_L10N_N3P3_M2P129_708 AY39 LPDDR4_2_CH1_DQ_A[8] IO_L22N_N7P3_M2P99_707 AW38 LPDDR4_2_CH1_DQ_A[9] IO_L22P_N7P2_M2P98_707 AD40 LPDDR4_2_CH1_DQ_B[0] IO_L19P_N6P2_M2P146_708 AF40 LPDDR4_2_CH1_DQ_B[1] IO_L22P_N7P2_M2P152_708 AY41 LPDDR4_2_CH1_DQ_B[10] IO_L7N_N2P3_M2P69_707 AY45 LPDDR4_2_CH1_DQ_B[11] IO_L11N_N3P5_M2P77_707 BA45 LPDDR4_2_CH1_DQ_B[12] IO_L11P_N3P4_M2P76_707 BA44 LPDDR4_2_CH1_DQ_B[13] IO_L10N_N3P3_M2P75_707 BA43 LPDDR4_2_CH1_DQ_B[14]...
  • Page 49 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number LPDDR4_3_CH0_CA_B[2] IO_L8N_N2P5_M3P125_711 LPDDR4_3_CH0_CA_B[3] IO_L8P_N2P4_M3P124_711 LPDDR4_3_CH0_CA_B[4] IO_L10N_N3P3_M3P129_711 LPDDR4_3_CH0_CA_B[5] IO_L10P_N3P2_M3P128_711 LPDDR4_3_CH0_CK_C_A[0] IO_L3N_XCC_N1P1_M3P115_711 LPDDR4_3_CH0_CK_C_B[0] IO_L9N_GC_XCC_N3P1_M3P127_711 LPDDR4_3_CH0_CK_T_A[0] IO_L3P_XCC_N1P0_M3P114_711 LPDDR4_3_CH0_CK_T_B[0] IO_L9P_GC_XCC_N3P0_M3P126_711 LPDDR4_3_CH0_CKE_A[0] IO_L5P_N1P4_M3P118_711 LPDDR4_3_CH0_CKE_A[1] IO_L5N_N1P5_M3P119_711 LPDDR4_3_CH0_CKE_B[0] IO_L11P_N3P4_M3P130_711 LPDDR4_3_CH0_CKE_B[1] IO_L7N_N2P3_M3P123_711 LPDDR4_3_CH0_CS_A[0] IO_L2P_N0P4_M3P112_711 LPDDR4_3_CH0_CS_A[1] IO_L0N_XCC_N0P1_M3P109_711 LPDDR4_3_CH0_CS_B[0]...
  • Page 50 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number LPDDR4_3_CH0_DQ_B[0] IO_L22P_N7P2_M3P98_710 LPDDR4_3_CH0_DQ_B[1] IO_L23P_N7P4_M3P100_710 LPDDR4_3_CH0_DQ_B[10] IO_L23P_N7P4_M3P154_711 LPDDR4_3_CH0_DQ_B[11] IO_L22P_N7P2_M3P152_711 LPDDR4_3_CH0_DQ_B[12] IO_L20N_N6P5_M3P149_711 LPDDR4_3_CH0_DQ_B[13] IO_L19N_N6P3_M3P147_711 LPDDR4_3_CH0_DQ_B[14] IO_L20P_N6P4_M3P148_711 LPDDR4_3_CH0_DQ_B[15] IO_L19P_N6P2_M3P146_711 LPDDR4_3_CH0_DQ_B[2] IO_L22N_N7P3_M3P99_710 LPDDR4_3_CH0_DQ_B[3] IO_L23N_N7P5_M3P101_710 LPDDR4_3_CH0_DQ_B[4] IO_L20N_N6P5_M3P95_710 LPDDR4_3_CH0_DQ_B[5] IO_L19P_N6P2_M3P92_710 LPDDR4_3_CH0_DQ_B[6] IO_L19N_N6P3_M3P93_710 LPDDR4_3_CH0_DQ_B[7] IO_L20P_N6P4_M3P94_710 LPDDR4_3_CH0_DQ_B[8]...
  • Page 51 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number LPDDR4_3_CH1_CA_B[5] IO_L8P_N2P4_M3P16_709 LPDDR4_3_CH1_CK_C_A[0] IO_L21N_XCC_N7P1_M3P43_709 LPDDR4_3_CH1_CK_C_B[0] IO_L9N_GC_XCC_N3P1_M3P19_709 LPDDR4_3_CH1_CK_T_A[0] IO_L21P_XCC_N7P0_M3P42_709 LPDDR4_3_CH1_CK_T_B[0] IO_L9P_GC_XCC_N3P0_M3P18_709 LPDDR4_3_CH1_CKE_A[0] IO_L23P_N7P4_M3P46_709 LPDDR4_3_CH1_CKE_A[1] IO_L18N_XCC_N6P1_M3P37_709 LPDDR4_3_CH1_CKE_B[0] IO_L6N_GC_XCC_N2P1_M3P13_709 LPDDR4_3_CH1_CKE_B[1] IO_L6P_GC_XCC_N2P0_M3P12_709 LPDDR4_3_CH1_CS_A[0] IO_L18P_XCC_N6P0_M3P36_709 LPDDR4_3_CH1_CS_A[1] IO_L23N_N7P5_M3P47_709 LPDDR4_3_CH1_CS_B[0] IO_L15N_XCC_N5P1_M3P31_709 LPDDR4_3_CH1_CS_B[1] IO_L0N_XCC_N0P1_M3P1_709 LPDDR4_3_CH1_DMI_A[0] IO_L15P_XCC_N5P0_M3P30_709 LPDDR4_3_CH1_DMI_A[1]...
  • Page 52 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number LPDDR4_3_CH1_DQ_B[11] IO_L5N_N1P5_M3P65_710 LPDDR4_3_CH1_DQ_B[12] IO_L1P_N0P2_M3P56_710 LPDDR4_3_CH1_DQ_B[13] IO_L1N_N0P3_M3P57_710 LPDDR4_3_CH1_DQ_B[14] IO_L2P_N0P4_M3P58_710 LPDDR4_3_CH1_DQ_B[15] IO_L2N_N0P5_M3P59_710 LPDDR4_3_CH1_DQ_B[2] IO_L2N_N0P5_M3P5_709 LPDDR4_3_CH1_DQ_B[3] IO_L2P_N0P4_M3P4_709 LPDDR4_3_CH1_DQ_B[4] IO_L5N_N1P5_M3P11_709 LPDDR4_3_CH1_DQ_B[5] IO_L1N_N0P3_M3P3_709 LPDDR4_3_CH1_DQ_B[6] IO_L4P_N1P2_M3P8_709 LPDDR4_3_CH1_DQ_B[7] IO_L5P_N1P4_M3P10_709 LPDDR4_3_CH1_DQ_B[8] IO_L4N_N1P3_M3P63_710 LPDDR4_3_CH1_DQ_B[9] IO_L4P_N1P2_M3P62_710 LPDDR4_3_CH1_DQS_C_A[0] IO_L12N_GC_XCC_N4P1_M3P25_709 LPDDR4_3_CH1_DQS_C_A[1]...
  • Page 53 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number PCIE_LCL_REFCLK_PIN_N GTYP_LPD_REFCLKN0_103 MGT REFCLK PCIE_LCL_REFCLK_PIN_P GTYP_LPD_REFCLKP0_103 MGT REFCLK PCIE_REFCLK_0_PIN_N GTYP_LPD_REFCLKN0_102 MGT REFCLK PCIE_REFCLK_0_PIN_P GTYP_LPD_REFCLKP0_102 MGT REFCLK PCIE_REFCLK_1_PIN_N GTYP_LPD_REFCLKN0_104 MGT REFCLK PCIE_REFCLK_1_PIN_P GTYP_LPD_REFCLKP0_104 MGT REFCLK PCIE_RST_1V8_L PMC_MIO38_501 PCIE_RST_1V8_L PMC_MIO39_501 PCIE_RX0_N...
  • Page 54 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number PCIE_RX8_N GTYP_LPD_RXN0_104 PCIE_RX8_P GTYP_LPD_RXP0_104 PCIE_RX9_N GTYP_LPD_RXN1_104 PCIE_RX9_P GTYP_LPD_RXP1_104 PCIE_TX0_PIN_N GTYP_LPD_TXN0_102 PCIE_TX0_PIN_P GTYP_LPD_TXP0_102 PCIE_TX1_PIN_N GTYP_LPD_TXN1_102 PCIE_TX1_PIN_P GTYP_LPD_TXP1_102 PCIE_TX10_PIN_N GTYP_LPD_TXN2_104 PCIE_TX10_PIN_P GTYP_LPD_TXP2_104 PCIE_TX11_PIN_N GTYP_LPD_TXN3_104 PCIE_TX11_PIN_P GTYP_LPD_TXP3_104 PCIE_TX12_PIN_N GTYP_LPD_TXN0_105 PCIE_TX12_PIN_P GTYP_LPD_TXP0_105 PCIE_TX13_PIN_N...
  • Page 55 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number PERST_PL_L IO_L8N_N2P5_712 PMOD_IO1_1V5 IO_L20P_N6P4_712 PMOD_IO2_1V5 IO_L20N_N6P5_712 PMOD_IO3_1V5 IO_L21P_XCC_N7P0_712 PMOD_IO4_1V5 IO_L21N_XCC_N7P1_712 PMOD_IO5_1V5 IO_L22P_N7P2_712 PMOD_IO6_1V5 IO_L22N_N7P3_712 PMOD_IO7_1V5 IO_L23P_N7P4_712 PMOD_IO8_1V5 IO_L23N_N7P5_712 QSFP0_LPMODE_1V1 IO_L26P_N8P4_M3P52_709 QSFP0_RESET_1V1_L IO_L25N_N8P3_M3P51_709 BL44 QSFP0_RX0_N GTYP_RXN0_201 BK44 QSFP0_RX0_P GTYP_RXP0_201 BN45...
  • Page 56 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BG43 QSFP0_TX3_P GTYP_TXP3_201 BK36 QSFP0_TX4_N GTYP_TXN0_200 BJ36 QSFP0_TX4_P GTYP_TXP0_200 BH37 QSFP0_TX5_N GTYP_TXN1_200 BG37 QSFP0_TX5_P GTYP_TXP1_200 BK38 QSFP0_TX6_N GTYP_TXN2_200 BJ38 QSFP0_TX6_P GTYP_TXP2_200 BH39 QSFP0_TX7_N GTYP_TXN3_200 BG39 QSFP0_TX7_P GTYP_TXP3_200 QSFP1_LPMODE_1V1 IO_L26P_N8P4_M3P106_710...
  • Page 57 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number BF49 QSFP1_TX3_P GTM_TXP3_202 BE48 QSFP1_TX4_N GTM_TXN0_203 BE47 QSFP1_TX4_P GTM_TXP0_203 BD50 QSFP1_TX5_N GTM_TXN1_203 BD49 QSFP1_TX5_P GTM_TXP1_203 BC48 QSFP1_TX6_N GTM_TXN2_203 BC47 QSFP1_TX6_P GTM_TXP2_203 BB50 QSFP1_TX7_N GTM_TXN3_203 BB49 QSFP1_TX7_P GTM_TXP3_203 AN44 QSFP2_LPMODE_1V1...
  • Page 58 ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AH49 QSFP2_TX3_P GTM_TXP3_205 BA48 QSFP2_TX4_N GTM_TXN0_204 BA47 QSFP2_TX4_P GTM_TXP0_204 AY50 QSFP2_TX5_N GTM_TXN1_204 AY49 QSFP2_TX5_P GTM_TXP1_204 AV50 QSFP2_TX6_N GTM_TXN2_204 AV49 QSFP2_TX6_P GTM_TXP2_204 AT50 QSFP2_TX7_N GTM_TXN3_204 AT49 QSFP2_TX7_P GTM_TXP3_204 QSPI0_CLK_PIN PMC_MIO0_500...

  • Page 59: Table

    ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number AJ48 SI5344_OUT1_PIN_N GTM_REFCLKN0_202 MGT REFCLK AJ47 SI5344_OUT1_PIN_P GTM_REFCLKP0_202 MGT REFCLK AR48 SI5344_OUT2_PIN_N GTYP_REFCLKN0_201 MGT REFCLK AR47 SI5344_OUT2_PIN_P GTYP_REFCLKP0_201 MGT REFCLK SI5344_RST_1V5_N IO_L18N_XCC_N6P1_712 SI5344_SCL_1V5 IO_L17N_N5P5_712 SI5344_SDA_1V5 IO_L17P_N5P4_712 SI5402_1V5_SCL IO_L8P_N2P4_712 SI5402_1V5_SDA...

  • Page 60: Table

    ADM-PA120 User Manual Signal Name Pin Name IO Voltage Bank Number TRIG_OUT_EN_FPGA IO_L11N_N3P5_712 TRIG_OUT_FPGA IO_L25N_N8P3_712 TRIG_TE_EN_FPGA IO_L24N_GC_XCC_N8P1_712 UART0_RXD PMC_MIO42_501 UART0_TXD PMC_MIO43_501 UART1_RXD PMC_MIO47_501 UART1_TXD PMC_MIO46_501 USB_ULPI_CLK_PIN PMC_MIO18_500 USB_ULPI_DATA[0]_PIN PMC_MIO14_500 USB_ULPI_DATA[1]_PIN PMC_MIO15_500 USB_ULPI_DATA[2]_PIN PMC_MIO16_500 USB_ULPI_DATA[3]_PIN PMC_MIO17_500 USB_ULPI_DATA[4]_PIN PMC_MIO19_500 USB_ULPI_DATA[5]_PIN PMC_MIO20_500 USB_ULPI_DATA[6]_PIN...
  • Page 61 ADM-PA120 User Manual Revision History Date Revision Changed By Nature of Change Initial Release. 30 Jun 2023 K. Roth Clarifyied that ToD input is also 1PPS in Introduction, corrected multiple naming mistakes in Clock Topology, Correct blank cells within Map, section G.703 Time of...

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