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Related Manuals for Alpha Data ADM-XRC-9R4
Summary of Contents for Alpha Data ADM-XRC-9R4
- Page 1 ADM-XRC-9R4 User Manual Document Revision: 1.1 8th June 2023...
- Page 2 ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 © 2023 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.
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Page 3: Table Of Contents
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Table Of Contents Introduction ............................1 Key Features ..........................1 Order Code ............................ 3 References & Specifications ......................3 Example Design ..........................4 Installation ............................5 Hardware Installation ........................5 3.1.1 Handling Instructions ......................... 5 3.1.2... - Page 4 Table 27 Pn4 Interface ............................ 32 List of Figures Figure 1 ADM-XRC-9R4 Board ........................1 Figure 2 ADM-XRC-9R4 Vivado Example Design ................... 4 Figure 3 ADM-XRC-9R4 Block Diagram ......................7 Figure 4 LED Locations ............................ 9 Figure 5 JTAG Boundary Scan Chain ......................11 Figure 6 Full Clock Diagram ...........................
- Page 5 Figure 15 Front Panel Pinout ........................... 20 Figure 16 ADM-XRC-9R4 ADC Frequency Response ..................22 Figure 17 ADM-XRC-9R4 ADC SFDR vs Signal Power .................. 22 Figure 18 ADM-XRC-9R4 ADC Input Matching ....................23 Figure 19 ADM-XRC-9R4 ADC Crosstalk ......................23 Figure 20 ADM-XRC-9R4 ADC Phase Matching .....................
- Page 6 ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Page Intentionally left blank...
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Page 7: Introduction
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 1 Introduction The ADM-XRC-9R4 is a high-performance XMC for applications using Zynq Ultrascale+ RFSoC DFE from Xilinx. Figure 1 : ADM-XRC-9R4 Board 1.1 Key Features Key Features • Single-width XMC, compliant to VITA Standard 42.0 and 42.10d12 •... - Page 8 ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 • Processing System (PS) Block consisting of: • Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU • 1 bank of DDR4-2400 SDRAM 2GB • Removable microSD Flash memory • Two Quad SPI Flash memory, 512Mb each •...
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Page 9: Order Code
/X2 = Vita 61 connectors /V88 = Vita 88 connectors Table 1 : Build Options Not all combinations are available. Please check with Alpha Data sales for details. 1.3 References & Specifications ANSI/VITA 42.0 XMC Standard, December 2008, VITA, ISBN 1-885731-49-3 ANSI/VITA 42.2... -
Page 10: Example Design
RF clocks, drive signals from the DACs, receive data from the ADCs, control the RF converter settings using the Xilinx XRFDC API and set the DSA attenuation. Figure 2 : ADM-XRC-9R4 Vivado Example Design Page 4 Example Design... -
Page 11: Installation
- Store in ESD safe bag. 3.1.2 Motherboard / Carrier Requirements The ADM-XRC-9R4 is a single width XMC.3 mezzanine with P6 and P4 connectors. The motherboard/ carrier must comply with the XMC.3 specification for the Primary XMC connector, J5. The Secondary XMC connector, P6 has a pinout compatible with various XMC to VPX signal maps as defined by VITA 46.9. -
Page 12: Cooling Requirements
The power dissipation of the board is highly dependent on the Target FPGA application. A power estimator spreadsheet is available on request from Alpha Data. This should be used in conjunction with Xilinx power estimation tools to determine the exact current requirements for each power rail. -
Page 13: Functional Description
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4 Functional Description 4.1 Overview Figure 3 : ADM-XRC-9R4 Block Diagram Functional Description Page 7 ad-ug-1481_v1_1.pdf... -
Page 14: Switch Definitions
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.1.1 Switch Definitions There is a set of eight DIP switches placed on the rear of the board. Their functions are described in Switch Definitions. Note: SW1-5 and SW1-8 are OFF by default. Factory Configuration switch must be in the OFF position for normal operation. -
Page 15: Led Definitions
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.1.2 LED Definitions The position and description of the board status LEDs are shown in Locations: Figure 4 : LED Locations Comp. Ref. Function ON State Off State D7(Amber) MVMRO Inhibit writes to non-volatile memories... -
Page 16: Xmc Platform Interface
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.2 XMC Platform Interface 4.2.1 IPMI I2C A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. This memory contains board information (type, voltage requirements etc.) as defined in the XMC based specification. -
Page 17: Jtag Interface
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.3 JTAG Interface 4.3.1 On-board Interface A JTAG boundary scan chain is connected to header U12. This allows the connection of the Xilinx JTAG cable for FPGA debug using the Xilinx ChipScope tools. -
Page 18: Clocks
V1.1 - 8th June 2023 4.4 Clocks The ADM-XRC-9R4 provides a wide variety of clocking options. The board has a user-programmable clock generator. These clocks can be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols. -
Page 19: 300Mhz Reference Clocks (Refclk300M And Fabric_Clk)
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.4.1 300MHz Reference Clocks (REFCLK300M and FABRIC_CLK) The fixed 300MHz reference clocks REFCLK300M and FABRIC_CLK are differential LVDS signals. REFCLK300M is used as the input clock for both DDR4 SDRAM interfaces. FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYCTRL). -
Page 20: Mgt Reference Clocks
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.4.5 MGT Reference Clocks The PS and PL MGTs can be clocked by sources from the P5, P6 or on-board clock sources Figure 7 : MGT Clocks 4.4.6 PS System Clock There PS is clocked by a fixed oscillator. -
Page 21: Rf Sampling Clocks
4.4.7 RF Sampling Clocks The RF reference clocks are generated with a dual-loop jitter cleaner PLL. The RF sampling clocks are using the on-chip PLLs in the RFSoC. Figure 8 : ADM-XRC-9R4 RF sampling clocks Source Frequency External Reference Clock 0.1 - 500MHz... -
Page 22: Sysref Clocks
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.4.7.1 Sysref Clocks The sysref clocks provide the sysref functionality to synchronize the RF DACs and ADCs. They are provided by the RF clock generators. They are connected to the PL and the RF sampling block. -
Page 23: Zynq Ps Block
4.5.4 PS DDR4 Memory The ADM-XRC-9R4 is fitted with one bank of PS DDR4 SDRAM. The bank is made up of a two 16-bit wide memory devices in parallel to provide a 32-bit datapath capable of running up to 1200MHz (DDR4-2400). 8Gbit devices (Micron MT40A512M16HA-083) are fitted as standard to provide 2GByte of memory. -
Page 24: Interfaces
The Target FPGA IO is arranged in banks, each with their own supply pins. The bank numbers, their voltage and function are shown in Target FPGA IO Banks. Full details of the IOSTANDARD required for each signal are given in the ADM-XRC-9R4 example design. IO Banks Voltage Purpose 3.3V... -
Page 25: Memory Interfaces
V1.1 - 8th June 2023 4.6.3 Memory Interfaces The ADM-XRC-9R4 has one banks of PL DDR4 SDRAM. The bank consists of one 8-bit wide memory device capable of running at up to 1200MHz (DDR-2400). 8Gbit devices (Micron MT40A1G8PM-083E) are fitted as standard. -
Page 26: Rf Interfaces
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.7 RF Interfaces 4.7.1 Front-Panel I/O The front panel interface consists of 5 MCX connectors J14, J15, J16, J17 and J19. Figure 13 : Front Panel RF IO Figure 14 : ADC Signal Path Figure 15 : Front Panel Pinout The ADC voltages in the table below are the single ended voltages at the RF connector. -
Page 27: Rf Performance
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.7.2 RF Performance 4.7.2.1 ADC RF Performance Measurement Conditions/Comments Value Unit Resolution Bits Sample Rate 1.0 - 5.9 GS/s Full Scale Input DSA attenuation = 0dB Vpk-pk Full Scale Input DSA attenuation = 0dB... -
Page 28: Figure 16 Adm-Xrc-9R4 Adc Frequency Response
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Figure 16 : ADM-XRC-9R4 ADC Frequency Response Figure 17 : ADM-XRC-9R4 ADC SFDR vs Signal Power Page 22 Functional Description ad-ug-1481_v1_1.pdf... -
Page 29: Figure 18 Adm-Xrc-9R4 Adc Input Matching
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Figure 18 : ADM-XRC-9R4 ADC Input Matching Figure 19 : ADM-XRC-9R4 ADC Crosstalk Functional Description Page 23 ad-ug-1481_v1_1.pdf... -
Page 30: Dac Rf Performance
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Figure 20 : ADM-XRC-9R4 ADC Phase Matching 4.7.2.2 DAC RF Performance Measurement Conditions/Comments Value Unit Resolution Bits Sample Rate 0.5 - 10.0 GS/s Voltage out of RF connector, 40.5mA, 50R Full Scale Output... -
Page 31: Figure 21 Adm-Xrc-9R4 Dac Frequency Response
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Figure 21 : ADM-XRC-9R4 DAC Frequency Response Functional Description Page 25 ad-ug-1481_v1_1.pdf... -
Page 32: Configuration
Monitoring. 4.9 System Monitoring The ADM-XRC-9R4 has the ability to monitor temperature and voltage to maintain a check on the operation of the board. The monitoring is implemented using the Atmel AVR microcontroller. Control algorithms within the microcontroller automatically check line voltages and on board temperatures and shares the information with the PS. -
Page 33: Automatic Temperature Monitoring
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 4.9.1 Automatic Temperature Monitoring At power-up, the control logic sets the temperature limits and resets the LM87's over-temperature interrupt. The temperature limits are shown in Table Temperature Limits: FPGA Board Commercial 0 degC... -
Page 34: System Monitor Interfaces
V1.1 - 8th June 2023 4.9.3 System Monitor Interfaces There are two ways to communicate with the System Monitor to retrieve board status information on the ADM-XRC-9R4. One is through the Micro USB connector (shown in <ERROR>USB Interfaces), the other is... -
Page 35: Appendix A Rear Connector Pinouts
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Appendix A: Rear Connector Pinouts Appendix A.1: Primary XMC Connector, P5 PN5_P0 PN5_N0 PN5_P1 PN5_N1 VPWR MRSTI_L PN5_P2 PN5_N2 PN5_P3 PN5_N3 VPWR MRSTO_L* VPWR 12V0 VPWR M12V0 VPWR PER_P0 PER_N0 MBIST_L* PER_P1... -
Page 36: Secondary Xmc Connector, P6
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Appendix A.2: Secondary XMC Connector, P6 PN6_DP_GPI PN6_DP_GPI PN6_DP_GPI PN6_DP_GPI GPIO14 GPIO8 O0_N O0_P O1_N O1_P ERROR PN6_DP_GPI PN6_DP_GPI PN6_DP_GPI PN6_DP_GPI ERROR O2_N O2_P O3_N O3_P ERROR PN6_DP_GPI PN6_DP_GPI PN6_DP_GPI PN6_DP_GPI GPIO13... -
Page 37: Pn6 Gpio Pin Map
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Appendix A.2.1: Pn6 GPIO Pin Map Signal P6 Pin FPGA Pin FPGA Bank GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 Table 26 : Pn6 GPIO Pin Map... -
Page 38: Pmc Connector P4
ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Appendix A.3: PMC Connector P4 Signal P4 Pin P4 Pin Signal GPIO14 GPIO8 GPIO13 GPIO12 GPIO7 GPIO11 GPIO6 GPIO10 GPIO5 GPIO9 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 COM1_RXD COM1_TXD Table 27 : Pn4 Interface... - Page 39 ADM-XRC-9R4 User Manual V1.1 - 8th June 2023 Revision History Date Revision Nature of Change Section(s) 19 Apr 2023 Copied/updated from 9R1 user guide. 16 May 2023 First release Removed dead link to heatsink environmental specifications 08 Jun 2023 ERROR...
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