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Related Manuals for Alpha Data ADA-VPX3-7V1
Summary of Contents for Alpha Data ADA-VPX3-7V1
- Page 1 ADA-VPX3-7V1 User Manual Document Revision: 2.1 6th January 2016...
- Page 2 ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 © 2016 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.
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Page 3: Table Of Contents
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Table Of Contents Introduction ............................1 Key Features ..........................1 References & Specifications ......................2 Installation ............................2 Software Installation ........................2 Hardware Installation ........................2 2.2.1 Handling Instructions ......................... 2 2.2.2 Cooling Requirements ....................... - Page 4 XRM Connector CN1, Field 3 ......................27 Table 21 XRM Connector CN2 ........................28 List of Figures Figure 1 ADA-VPX3-7V1 Block Diagram ......................4 Figure 2 XMC LED Locations .......................... 6 Figure 3 JTAG Header XMC-J1 ........................8 Figure 4 JTAG Boundary Scan Chain ......................
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Page 5: Introduction
(target) FPGA. With the release of 7series FPGA boards, Alpha Data has introduced a new build option to allow the mezzanine card to be assembled without the bridge to reduce power and cost. -
Page 6: References & Specifications
The power dissipation of the board is highly dependent on the Target FPGA application. A power estimator spreadsheet is available on request from Alpha Data. This should be used in conjunction with Xilinx power estimation tools to determine the exact current requirements for each power rail. - Page 7 V2.1 - 6th January 2016 metalwork for conduction cooled applications. For more details on heatsinks supplied with Alpha Data boards, please view AD-AN-0018 ADM-XRC Cooling Solutions. The board features system monitoring that measures the board and FPGA temperature. It also includes a self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is detected.
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Page 8: Functional Description
Note: The ADA-VPX3-7V1 is comprised of an ADM-XRC-7V1 XMC card mounted to an ADC-VPX3-XMC VPX carrier specifically designed to host Alpha Data XMCs. All reference to "XMC" refer to the ADM-XRC-7V1, while all references to "Carrier" refer to the ADC-VPX3-XMC. -
Page 9: Switch Definitions
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.1.1 Switch Definitions There are three sets of eight DIP switches. One is placed on the XMC card and the other two are on the VPX Carrier. Their functions are described in tables below. -
Page 10: Led Definitions
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.1.2 LED Definitions There are eight LEDs placed on the rear of the XMC board to indicate status: Status 1 Status 2 Target Done D10 Bridge Done D11 Bridge-Bypass D10 Bridge-Less Figure 2 : XMC LED Locations Comp. -
Page 11: Vpx P0 Interface
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.2 VPX P0 Interface 3.2.1 MVMRO Non-Volatile Memory Read Only. This signal is an input from the system. When asserted (high), all writes to non-volatile memories are inhibited. This is indicated by the Amber LED, XMC-D7. -
Page 12: Jtag Interface
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.3 JTAG Interface 3.3.1 On-board Interface A JTAG boundary scan chain is connected to header XMC-J1. This allows the connection of the Xilinx JTAG cable for FPGA debug using the Xilinx ChipScope tools. -
Page 13: Clocks
4 user-programmable clocks. These clocks can be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols. A complete overview of the clock routing on the ADA-VPX3-7V1 is given in Figure Clocks. A description of each clock follows. -
Page 14: Pcie Reference Clock 0 (Pcierefclk0)
MGT signal inputs. Most needed reference clocks can be generated through the User Programmable clocking options. If it is a requirement that this differential pair be utilized as a clock signal to an MGT bank, a resistor fit option is available. Please contact Alpha Data for detials. Page 10 Functional Description ad-ug-1260_v2_1.pdf... -
Page 15: Auxclk
There are two programable clock sources that are forwarded throughout the FPGA. These clocks are programmable through the Alpha Data ADM-XRC Gen 3 SDK. LCLK is generated in the Bridge FPGA by the the Alpha Data ADB3 driver and offers a less accurate frequency resolution, but with a wider programmable frequency range. -
Page 16: Xrm Lvds Clock (Xrm_Lvds_Clk)
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.4.8 XRM LVDS Clock (XRM_LVDS_CLK) The clock "XRM_LVDS_CLK" is a differential clock signal using LVDS levels. The clock is provided by the target FPGA and connected to an XRM module through the XRM connector, CN1, at pins 113 & 115. -
Page 17: Flash Memory
FLPAGE and FLDATA registers in the Bridge FPGA. The region of memory between addresses 0x11000000 and 0x11FFFFF is allocated for custom data to be stored by the ADA-VPX3-7V1 user. Utilities for erasing, programming and verification of the flash memory are provided in the ADMXRC SDK. -
Page 18: Configuration
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.6 Configuration 3.6.1 Power-Up Sequence If valid data is stored in the flash memory, the bridge will automatically configure the Target FPGA at power-up. This sequence can be inhibited by turning the Flash Boot Inhibit (FBI) switch, SW1-5 to ON. (See Table XMC SW1 Definitions). -
Page 19: Health Monitoring
V2.1 - 6th January 2016 3.7 Health Monitoring The ADA-VPX3-7V1 has the ability to monitor temperature and voltage to maintain a check on the operation of the board. The monitoring is implemented using the ATMEGA128 microcontroller. Control algorithms within the microcontroller automatically check line voltages and on board temperaturs and shares the information with blockram in the Bridge FPGA. -
Page 20: Automatic Temperature Monitoring
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.7.1 Automatic Temperature Monitoring At power-up, the control logic sets the temperature limits and resets the LM87's over-temperature interrupt. The temperature limits are shown in Table Temperature Limits: Target FPGA Bridge FPGA... -
Page 21: Local Bus
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.8 Local Bus A Multiplexed Packet Transport Link (MPTL) connects the Bridge and Target FPGAs. It is capable of transferring data at up to 2GB/s simultaneously in each direction. The MPTL replaces the parallel local bus used in previous generations of the ADM-XRC series. Details of the link and example designs are given in the Software Development Kit (SDK). -
Page 22: Memory Interfaces
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 7 Series MGT/ Banks MGT119 PCIe Bridge VPX P1 MGT118 RearMGT(3:0) Wafers 1-4 RearMGT(7:4) Bridge Bypass Wafers 5-8 MGT117 RearMGT(11:8) Wafers 9-12 MGT115 RearMGT(13:12) Wafers 15-16 MGT116 Dual RearMGT(15:14) MSATA Sites MGT114... -
Page 23: Table
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 devices (Micron MT41J64M16-187E) are fitted as standard to provide 512MB per bank. 4Gb (giving 1GB per bank) are available as an ordering option. The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator (MIG). -
Page 24: Xrm Interface And Front-Panel I/O
The XRM interface provides a high-performance and flexible front-panel interface through a range of interchangeable XRM modules. Further details of the XRM modules can be found on the Alpha Data website. The XRM interface consists of two samtec connectors, CN1 and CN2. -
Page 25: Xrm I/F - High-Speed Serial Links
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 3.11.4 XRM I/F - High-speed Serial Links Eight MGT links are routed between the Target FPGA and the XRM interface. Lanes (6:0) are routed through the Samtec QSE-DP connector, CN2. Lane (7) is routed through the Samtec QSH connector, CN1. - Page 26 ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Page Intentionally left blank Page 22 Functional Description ad-ug-1260_v2_1.pdf...
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Page 27: Appendix A Vpx Backplane Pinouts
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Appendix A: VPX Backplane Pinouts Download the complete pinout csv from http://www.alpha-data.com/esp/products.php?product=ada-vpx3-7v1 VPX Backplane Pinouts Page 23 ad-ug-1260_v2_1.pdf... -
Page 28: Appendix B Front (Xrm) Connector Pinouts
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Appendix B: Front (XRM) Connector Pinouts The XRM interface consists of two connectors: CN1 and CN2. CN1 is a 180-way Samtec QSH in 3 fields. It is for general-purpose signals, power and module control. CN2 is a 28-way Samtec QSE-DP for high-speed serial (MGT) links. -
Page 29: Xrm Connector Cn1, Field 1
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Appendix B.1: XRM Connector CN1, Field 1 Signal FPGA Samtec Samtec FPGA Signal DA_N0 AE35 AD31 DA_N1 DA_P0 AE34 AC31 DA_P1 DA_N2 AB31 DA_P3 DA_P2 AB32 DA_N3 DA_N4 AE33 DA_N5 DA_P4 AE32... -
Page 30: Xrm Connector Cn1, Field 2
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Appendix B.2: XRM Connector CN1, Field 2 Signal FPGA Samtec Samtec FPGA Signal DB_N2 AD37 AV41 DB_N3 DB_P2 AD36 AU41 DB_P3 DB_N4 AA37 AH36 DB_N5 DB_P4 AG36 DB_P5 DB_N6 AG34 AW42 DB_N7... -
Page 31: Xrm Connector Cn1, Field 3
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Appendix B.3: XRM Connector CN1, Field 3 Signal FPGA Samtec Samtec FPGA Signal DC_P2 AP41 AR38 DC_P3 DC_N2 AP42 AR39 DC_N3 DC_N4 BB39 AW37 DC_P5 DC_P4 BB38 AY37 DC_N5 DC_P6 AR42 AY39... -
Page 32: Xrm Connector Cn2
ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Appendix B.4: XRM Connector CN2 Signal FPGA Samtec Samtec FPGA Signal MGT_C2M_P0 MGT_M2C_P0 MGT_C2M_N0 MGT_M2C_N0 MGT_C2M_P1 MGT_M2C_P1 MGT_C2M_N1 MGT_M2C_N1 MGT_C2M_P4 MGT_M2C_P4 MGT_C2M_N4 MGT_M2C_N4 MGT_C2M_P5 MGT_M2C_P5 MGT_C2M_N5 MGT_M2C_N5 MGT_C2M_P2 MGT_M2C_P2 MGT_C2M_N2 MGT_M2C_N2 MGT_C2M_P3... - Page 33 ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Revision History Date Revision Changed By Nature of Change Initial Draft 17 Oct 2012 K. Roth Initial Release 6 Feb 2013 K. Roth Updated tables and figures to align with ADM-XRC-7V1 rev3 (ad_ug_1248 v1.5) and ADC-VPX3-XMC rev2 1 Aug 2014 K.
- Page 34 ADA-VPX3-7V1 User Manual V2.1 - 6th January 2016 Page Intentionally left blank Address: 4 West Silvermills Lane, Address: 3507 Ringsby Court Suite 105, Edinburgh, EH3 5BD, UK Denver, CO 80216 Telephone: +44 131 558 2600 Telephone: (303) 954 8768 Fax:...
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